riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

Date Created 2024-01-05 (6 months ago)
Commits 342 (last one 5 days ago)
Stargazers 37 (1 this week)
Watchers 17 (0 this week)
Forks 24
License cc-by-4.0
Ranking

RepositoryStats indexes 537,867 repositories, of these riscv/riscv-cheri is ranked #491,755 (9th percentile) for total stargazers, and #126,648 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #93,568/104,261.

Other Information

riscv/riscv-cheri has 13 open pull requests on Github, 157 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 38 open issues and 95 closed issues.

Homepage URL: https://jira.riscv.org/browse/RVG-148

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342 commits on the default branch (main) since jan '22

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The primary language is Python but there's also others...

updated: 2024-07-05 @ 09:25pm, id: 739559007 / R_kgDOLBTGXw