riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

Date Created 2024-01-05 (11 months ago)
Commits 442 (last one 12 days ago)
Stargazers 57 (1 this week)
Watchers 20 (0 this week)
Forks 30
License cc-by-4.0
Ranking

RepositoryStats indexes 589,134 repositories, of these riscv/riscv-cheri is ranked #426,533 (28th percentile) for total stargazers, and #110,797 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #81,212/117,584.

Other Information

riscv/riscv-cheri has 6 open pull requests on Github, 245 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 37 open issues and 152 closed issues.

Homepage URL: https://jira.riscv.org/browse/RVG-148

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442 commits on the default branch (main) since jan '22

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updated: 2024-12-03 @ 09:03am, id: 739559007 / R_kgDOLBTGXw