TinyTapeout / tt06-verilog-template

Submission template for Tiny Tapeout 6 - Verilog HDL Projects

TinyTapeout
TinyTapeout
Date Created 2024-01-05 (about a year ago)
Commits 17 (last one 11 months ago)
Stargazers 32 (0 this week)
Watchers 4 (0 this week)
Forks 180
License apache-2.0
This repository has been archived on Github
Ranking

RepositoryStats indexes 633,911 repositories, of these TinyTapeout/tt06-verilog-template is ranked #591,278 (7th percentile) for total stargazers, and #366,660 for total watchers. Github reports the primary language for this repository as Tcl, for repositories using this language it is ranked #133/139.

Other Information

Homepage URL: https://tinytapeout.com

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

17 commits on the default branch (main) since jan '22

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Yearly Commits

Commits to the default branch (main) per year

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Issue History

Total Issues
Open Issues
Closed Issues
332.52.5221.51.5110.50.500May '24May '24Jun '24Jun '24Jul '24Jul '24Aug '24Aug '24Sep '24Sep '24Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25

Languages

The primary language is Tcl but there's also others...

TclTclVerilogVerilogPythonPythonMakefileMakefile
Opengraph Image
TinyTapeout/tt06-verilog-template

updated: 2025-03-18 @ 09:00pm, id: 739495575 / R_kgDOLBPOlw