TinyTapeout / tt06-verilog-template

Submission template for Tiny Tapeout 6 - Verilog HDL Projects

TinyTapeout
TinyTapeout
Date Created 2024-01-05 (5 months ago)
Commits 17 (last one 2 months ago)
Stargazers 29 (0 this week)
Watchers 4 (0 this week)
Forks 174
License apache-2.0
This repository has been archived on Github
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RepositoryStats indexes 534,880 repositories, of these TinyTapeout/tt06-verilog-template is ranked #520,229 (3rd percentile) for total stargazers, and #354,941 for total watchers. Github reports the primary language for this repository as Tcl, for repositories using this language it is ranked #121/127.

Other Information

Homepage URL: https://tinytapeout.com

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17 commits on the default branch (main) since jan '22

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TinyTapeout/tt06-verilog-template

updated: 2024-06-27 @ 12:59am, id: 739495575 / R_kgDOLBPOlw