accellera-official / uvm-core

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accellera-official
accellera-official
Date Created 2023-06-06 (about a year ago)
Commits 18 (last one 7 months ago)
Stargazers 79 (0 this week)
Watchers 11 (0 this week)
Forks 21
License apache-2.0
Ranking

RepositoryStats indexes 635,117 repositories, of these accellera-official/uvm-core is ranked #361,404 (43rd percentile) for total stargazers, and #186,481 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #101/195.

Other Information

accellera-official/uvm-core has Github issues enabled, there are 2 open issues and 8 closed issues.

There have been 3 releases, the latest one was published on 2024-09-03 (7 months ago) with the name 1800.2 2020.3.1.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

18 commits on the default branch (main) since jan '22

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Yearly Commits

Commits to the default branch (main) per year

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Issue History

Total Issues
Open Issues
Closed Issues
101099887766554433221100Aug '23Aug '23Sep '23Sep '23Oct '23Oct '23Nov '23Nov '23Dec '23Dec '2320242024Feb '24Feb '24Mar '24Mar '24Apr '24Apr '24May '24May '24Jun '24Jun '24Jul '24Jul '24Aug '24Aug '24Sep '24Sep '24Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25Apr '25Apr '25

Languages

The primary language is SystemVerilog but there's also others...

SystemVerilogSystemVerilogCCC++C++

updated: 2025-03-26 @ 11:40am, id: 650226393 / R_kgDOJsGq2Q