Statistics for language SystemVerilog

Common SystemVerilog components

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.

No description

VeeR EL2 Core

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.

No description

VeeR EL2 Core

Common SystemVerilog components

A minimal GPU design in Verilog to learn how GPUs work from the ground up

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

Common SystemVerilog components

Send video/audio over HDMI on an FPGA

Sega Saturn for MiSTer

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

Sega Saturn for MiSTer

cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

A minimal GPU design in Verilog to learn how GPUs work from the ground up

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

OpenTitan: Open source silicon root of trust

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

NTUEE Digital Circuit Lab 24Fall

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...

A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI

The multi-core cluster of a PULP system.

Sega Saturn for MiSTer

A minimal GPU design in Verilog to learn how GPUs work from the ground up

A minimal Tensor Processing Unit (TPU) inspired by Google's TPUv1.

No description

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

No description

A minimal GPU design in Verilog to learn how GPUs work from the ground up

OpenTitan: Open source silicon root of trust

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

No description

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

No description

Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"

IOMMU IP compliant with the RISC-V IOMMU Specification v1.0