Statistics for language SystemVerilog
RepositoryStats tracks 616,884 Github repositories, of these 191 are reported to use a primary language of SystemVerilog.
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A minimal GPU design in Verilog to learn how GPUs work from the ground up
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
A minimal GPU design in Verilog to learn how GPUs work from the ground up
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card
A minimal GPU design in Verilog to learn how GPUs work from the ground up
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
A minimal GPU design in Verilog to learn how GPUs work from the ground up
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.