Statistics for language SystemVerilog
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A minimal GPU design in Verilog to learn how GPUs work from the ground up
Contains the code examples from The UVM Primer Book sorted by chapters.
The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)
A minimal GPU design in Verilog to learn how GPUs work from the ground up
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator based on a GeMM systolic array engine.
FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)
Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt
A minimal GPU design in Verilog to learn how GPUs work from the ground up
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
A minimal GPU design in Verilog to learn how GPUs work from the ground up
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
A minimal GPU design in Verilog to learn how GPUs work from the ground up
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt
SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator based on a GeMM systolic array engine.