Statistics for language SystemVerilog

A minimal GPU design in Verilog to learn how GPUs work from the ground up

Contains the code examples from The UVM Primer Book sorted by chapters.

AXI Adapter(s) for RISC-V Atomic Operations

Common SystemVerilog components

A Linux-capable RISC-V multicore for and by the world

AXI Adapter(s) for RISC-V Atomic Operations

IOMMU IP compliant with the RISC-V IOMMU Specification v1.0

RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.

VIP for AXI Protocol

A minimal GPU design in Verilog to learn how GPUs work from the ground up

A minimal GPU design in Verilog to learn how GPUs work from the ground up

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

Contains the code examples from The UVM Primer Book sorted by chapters.

RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.

Common SystemVerilog components

RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.

IOMMU IP compliant with the RISC-V IOMMU Specification v1.0

Atari STE MiSTery core for the Tang Nano 20k FPGA

AXI Adapter(s) for RISC-V Atomic Operations

No description

A minimal GPU design in Verilog to learn how GPUs work from the ground up

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

OpenTitan: Open source silicon root of trust

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Project F brings FPGAs to life with exciting open-source designs you can build on.

SystemVerilog language-oriented exercises

A minimal GPU design in Verilog to learn how GPUs work from the ground up

IOMMU IP compliant with the RISC-V IOMMU Specification v1.0

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

AXI Adapter(s) for RISC-V Atomic Operations

A minimal GPU design in Verilog to learn how GPUs work from the ground up

Atari STE MiSTery core for the Tang Nano 20k FPGA

Методические материалы по разработке процессора архитектуры RISC-V

A Fast, Low-Overhead On-chip Network

RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.

A minimal GPU design in Verilog to learn how GPUs work from the ground up

OpenTitan: Open source silicon root of trust

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Atari STE MiSTery core for the Tang Nano 20k FPGA

A Fast, Low-Overhead On-chip Network

Sega Saturn for MiSTer

A simple superscalar out of order RISC-V (micro)processor

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.