Statistics for language SystemVerilog

RepositoryStats tracks 616,884 Github repositories, of these 191 are reported to use a primary language of SystemVerilog.

Most starred repositories for language SystemVerilog (view more)

597
7.9k
unknown
72
A minimal GPU design in Verilog to learn how GPUs work from the ground up
Created 2024-04-09
90 commits to master branch, last one 9 months ago
812
2.7k
apache-2.0
110
OpenTitan: Open source silicon root of trust
Created 2019-08-26
25,925 commits to master branch, last one 3 hours ago
577
1.5k
apache-2.0
100
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Created 2017-08-08
2,793 commits to master branch, last one a day ago
275
1.2k
other
40
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Created 2018-04-12
1,318 commits to master branch, last one 27 days ago
26
1.2k
unknown
18
A Verilog synthesis flow for Minecraft redstone circuits
Created 2016-10-05
112 commits to master branch, last one 4 years ago
118
1.1k
other
47
Send video/audio over HDMI on an FPGA
Created 2019-08-17
306 commits to master branch, last one about a year ago

Trending repositories for language SystemVerilog (view more)