Statistics for language SystemVerilog

A minimal GPU design in Verilog to learn how GPUs work from the ground up

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.

No description

Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.

A minimal GPU design in Verilog to learn how GPUs work from the ground up

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

OpenTitan: Open source silicon root of trust

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

No description

32-bit 5-Stage Pipelined RISC V RV32I Core

A minimal GPU design in Verilog to learn how GPUs work from the ground up

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

OpenTitan: Open source silicon root of trust

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

The multi-core cluster of a PULP system.

No description

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

A minimal GPU design in Verilog to learn how GPUs work from the ground up

A minimal Tensor Processing Unit (TPU) inspired by Google's TPUv1.

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

No description

No description

A minimal GPU design in Verilog to learn how GPUs work from the ground up

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

OpenTitan: Open source silicon root of trust

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

No description

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator based on a GeMM systolic array engine.

Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.