fpganinja / taxi

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

fpganinja
fpganinja
Date Created 2025-02-03 (about a month ago)
Commits 196 (last one 4 days ago)
Stargazers 128 (13 this week)
Watchers 5 (0 this week)
Forks 18
License cern-ohl-s-2.0
Ranking

RepositoryStats indexes 630,459 repositories, of these fpganinja/taxi is ranked #259,517 (59th percentile) for total stargazers, and #323,396 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #66/196.

Other Information

fpganinja/taxi has Github issues enabled, there are 10 open issues and 0 closed issues.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

5555444444333308 Feb08 Feb16 Feb16 Feb24 Feb24 FebMar '25Mar '2508 Mar08 Mar16 Mar16 Mar

Recent Commit History

196 commits on the default branch (master) since jan '22

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Yearly Commits

Commits to the default branch (master) per year

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Issue History

Total Issues
Open Issues
Closed Issues
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Languages

The primary language is SystemVerilog but there's also others...

SystemVerilogSystemVerilogPythonPythonTclTclMakefileMakefileFortranFortranFilebench WMLFilebench WML

updated: 2025-03-23 @ 08:29pm, id: 926404139 / R_kgDONzfOKw