Statistics for topic systemverilog
RepositoryStats tracks 595,856 Github repositories, of these 90 are tagged with the systemverilog topic. The most common primary language for repositories using this topic is SystemVerilog (32). Other languages include: Verilog (20), Python (11)
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Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。
An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
Verilog implementation of PAL, NTSC and SECAM color encoding
A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPG...
Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https://na...
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
Методические материалы по разработке процессора архитектуры RISC-V
