Statistics for topic systemverilog

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

RISC-V Linux SoC, marchID: 0x2b

SystemVerilog to Verilog conversion

Send video/audio over HDMI on an FPGA

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

RISC-V Linux SoC, marchID: 0x2b

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SystemVerilog to Verilog conversion

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

RISC-V Linux SoC, marchID: 0x2b

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

An abstraction library for interfacing EDA tools

Package manager and build tool for HDLs

Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chili-chips.xyz/open-cologne

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Veryl: A Modern Hardware Description Language

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

A Single Cycle Risc-V 32 bit CPU

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

Control and status register code generator toolchain

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPG...

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chili-chips.xyz/open-cologne

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPG...

RISC-V Linux SoC, marchID: 0x2b

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Veryl: A Modern Hardware Description Language

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

A hardware component library developed with ROHD.

Методические материалы по разработке процессора архитектуры RISC-V

No description

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6