tscheipel / HaDes-V

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

Date Created 2024-12-14 (19 days ago)

Commits 3 (last one 15 days ago)

Stargazers 26 (1 this week)

Watchers 1 (0 this week)

Forks 1

License mit

Ranking

RepositoryStats indexes 599,932 repositories, of these tscheipel/HaDes-V is ranked #589,000 (2nd percentile) for total stargazers, and #547,874 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #182/183.

tscheipel/HaDes-V is also tagged with popular topics, for these it's ranked: risc-v (#267/271), riscv (#168/169)

Other Information

Homepage URL: https://www.scheipel.com/oer

All Topics

riscv rv32i risc-v vivado gtkwave pipelines verilator c-programming systemverilog open-education system-verilog processor-design university-course assembly-programming computer-architecture microcontroller-design processor-architecture hardware-software-codesign open-educational-resources

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3 commits on the default branch (main) since jan '22

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The primary language is SystemVerilog but there's also others...

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updated: 2024-12-30 @ 01:38am, id: 903381175 / R_kgDONdiAtw