tscheipel / HaDes-V

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

Date Created 2024-12-14 (2 months ago)

Commits 4 (last one about a month ago)

Stargazers 39 (0 this week)

Watchers 1 (0 this week)

Forks 2

License mit

Ranking

RepositoryStats indexes 624,936 repositories, of these tscheipel/HaDes-V is ranked #546,704 (13th percentile) for total stargazers, and #551,686 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #163/193.

tscheipel/HaDes-V is also tagged with popular topics, for these it's ranked: risc-v (#249/276), riscv (#161/178)

Other Information

Homepage URL: https://www.scheipel.com/oer

All Topics

riscv rv32i risc-v vivado gtkwave pipelines verilator c-programming systemverilog open-education system-verilog processor-design university-course assembly-programming computer-architecture microcontroller-design processor-architecture hardware-software-codesign open-educational-resources

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4 commits on the default branch (main) since jan '22

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The primary language is SystemVerilog but there's also others...

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updated: 2025-02-21 @ 08:31am, id: 903381175 / R_kgDONdiAtw