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opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Created
2018-08-19
282 commits to master branch, last one 6 days ago
A CPU implemented in a modular synthesizer
Created
2021-12-29
10 commits to main branch, last one 2 years ago
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clo...
Created
2018-10-31
10 commits to master branch, last one about a year ago