7 results found Sort:

293
2.2k
bsd-3-clause
94
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Created 2018-08-19
353 commits to master branch, last one a day ago
7
301
unknown
7
A CPU implemented in a modular synthesizer
Created 2021-12-29
10 commits to main branch, last one 2 years ago
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clo...
Created 2018-10-31
10 commits to master branch, last one 2 years ago
CPU Design Based on RISCV ISA
Created 2024-06-08
82 commits to main branch, last one 7 months ago
tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
Created 2020-10-02
143 commits to main branch, last one 3 years ago
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...
Created 2024-12-14
4 commits to main branch, last one 2 days ago
Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.
Created 2024-11-30
8 commits to main branch, last one about a month ago