4 results found Sort:

darklife
darkriscv darklife
286
2.1k
bsd-3-clause
94
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
cpu rtl core fpga riscv rv32e rv32i risc-v verilog softcore processor processor-design
Created 2018-08-19
343 commits to master branch, last one 9 days ago
katef
eurorack-cpu katef
7
300
unknown
7
A CPU implemented in a modular synthesizer
modular synthesizer cpu-emulator processor-design
Created 2021-12-29
10 commits to main branch, last one 2 years ago
zslwyuan
Basic-SIMD-Processor-Verilog-Tutorial zslwyuan
33
125
gpl-3.0
6
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clo...
alu cpu simd adder verilog processor multiplier verilog-project cadence-virtuoso processor-design instruction-set-architecture
Created 2018-10-31
10 commits to master branch, last one 2 years ago
peilin-chen
Zhulong-RISCV-CPU peilin-chen
18
76
mit
3
CPU Design Based on RISCV ISA
processor-design integrated-circuits
Created 2024-06-08
82 commits to main branch, last one 5 months ago