6 results found Sort:

darklife
darkriscv darklife
290
2.1k
bsd-3-clause
94
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
cpu rtl core fpga riscv rv32e rv32i risc-v verilog softcore processor processor-design
Created 2018-08-19
343 commits to master branch, last one about a month ago
katef
eurorack-cpu katef
7
300
unknown
7
A CPU implemented in a modular synthesizer
modular synthesizer cpu-emulator processor-design
Created 2021-12-29
10 commits to main branch, last one 2 years ago
zslwyuan
Basic-SIMD-Processor-Verilog-Tutorial zslwyuan
33
128
gpl-3.0
6
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clo...
alu cpu simd adder verilog processor multiplier verilog-project cadence-virtuoso processor-design instruction-set-architecture
Created 2018-10-31
10 commits to master branch, last one 2 years ago
peilin-chen
Zhulong-RISCV-CPU peilin-chen
20
82
mit
4
CPU Design Based on RISCV ISA
processor-design integrated-circuits
Created 2024-06-08
82 commits to main branch, last one 6 months ago
shehanmunasinghe
tinyGPU shehanmunasinghe
9
40
unknown
5
tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
gpu hdl simd systemverilog processor-design computer-organization
Created 2020-10-02
143 commits to main branch, last one 3 years ago
aofarmakis
Nibbling-bits aofarmakis
0
29
mit
1
Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.
verilog assembly assembler processor-design computer-architecture computer-organization single-cycle-processor instruction-set-architecture hardware-description-language
Created 2024-11-30
8 commits to main branch, last one 14 days ago