Statistics for topic verilog-project

RepositoryStats tracks 613,561 Github repositories, of these 9 are tagged with the verilog-project topic.

Stargazers over time for topic verilog-project

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Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and...
Created 2020-12-02
317 commits to main branch, last one 2 months ago
Image Processing Toolbox in Verilog using Basys3 FPGA
Created 2018-12-04
44 commits to master branch, last one about a year ago
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clo...
Created 2018-10-31
10 commits to master branch, last one 2 years ago
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion,...
Created 2022-01-14
102 commits to main branch, last one 2 years ago
Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
Created 2022-04-30
45 commits to main branch, last one 2 years ago
NSCSCC2022龙芯杯个人赛,MIPS32,59MHz经典五级流水线架构,易于初学者阅读(计算机组成原理,自己动手写CPU)
Created 2022-08-21
4 commits to main branch, last one 10 months ago

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