Statistics for topic verilog-project

RepositoryStats tracks 584,796 Github repositories, of these 9 are tagged with the verilog-project topic.

Stargazers over time for topic verilog-project

Most starred repositories for topic verilog-project (view more)

sudhamshu091
32-Verilog-Mini-Projects sudhamshu091
113
587
other
10
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and...
verilog miniproject verilog-hdl verilog-project
Created 2020-12-02
317 commits to main branch, last one 7 days ago
Gowtham1729
Image-Processing Gowtham1729
36
183
apache-2.0
4
Image Processing Toolbox in Verilog using Basys3 FPGA
coe ram fpga vhdl basys hsync pixel basys3 python vivado python3 verilog basys-board basys3-fpga convolution motion-blur verilog-hdl digital-systems verilog-project image-processing
Created 2018-12-04
44 commits to master branch, last one about a year ago
zslwyuan
Basic-SIMD-Processor-Verilog-Tutorial zslwyuan
33
125
gpl-3.0
6
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clo...
alu cpu simd adder verilog processor multiplier verilog-project cadence-virtuoso processor-design instruction-set-architecture
Created 2018-10-31
10 commits to master branch, last one 2 years ago
snbk001
Verilog-Design-Examples snbk001
16
95
unknown
1
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion,...
verilog testbenches verilog-hdl verilog-code self-checking verilog-design verilog-project verilog-programs
Created 2022-01-14
102 commits to main branch, last one 2 years ago
michaelehab
AES-Verilog michaelehab
20
81
unknown
2
Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
aes rtl fpga learn aes-128 aes-192 aes-256 verilog fpga-soc security encryption fpga-board verilog-hdl cryptography aes-decryption aes-encryption verilog-project encryption-decryption
Created 2022-04-30
45 commits to main branch, last one 2 years ago
xiazhuo
nscc2022_personal xiazhuo
3
53
mit
0
NSCSCC2022龙芯杯个人赛，MIPS32，59MHz经典五级流水线架构，易于初学者阅读（计算机组成原理，自己动手写CPU）
mips32 verilog-project nscscc2022-single
Created 2022-08-21
4 commits to main branch, last one 8 months ago

Trending repositories for topic verilog-project (view more)

Last 3 days (new repositories)
no newly created repositories trending in the last 3 days
Last 3 days (absolute gain)
no repositories trending in the last 3 days
Last 3 days (relative gain)
no repositories trending in the last 3 days
Last week (new repositories)
no newly created repositories trending in the last week
Last week (absolute gain)
sudhamshu091
sudhamshu091/32-Verilog-Mini-Projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and...

587 (+3)
snbk001
snbk001/Verilog-Design-Examples

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion,...

95 (+1)
Last week (relative gain)
snbk001
snbk001/Verilog-Design-Examples

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion,...

95 (+1%)
sudhamshu091
sudhamshu091/32-Verilog-Mini-Projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and...

587 (+0.5%)
Last month (new repositories)
no newly created repositories trending in the last month
Last month (absolute gain)
sudhamshu091
sudhamshu091/32-Verilog-Mini-Projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and...

587 (+15)
snbk001
snbk001/Verilog-Design-Examples

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion,...

95 (+4)
michaelehab
michaelehab/AES-Verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

81 (+3)
zslwyuan
zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clo...

125 (+2)
gpl-3.0
prajwalgekkouga
prajwalgekkouga/AHB-to-APB-Bridge

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equiva...

49 (+1)
Last month (relative gain)
snbk001
snbk001/Verilog-Design-Examples

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion,...

95 (+4%)
michaelehab
michaelehab/AES-Verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

81 (+4%)
sudhamshu091
sudhamshu091/32-Verilog-Mini-Projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and...

587 (+3%)
prajwalgekkouga
prajwalgekkouga/AHB-to-APB-Bridge

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equiva...

49 (+2%)
xiazhuo
xiazhuo/nscc2022_personal

NSCSCC2022龙芯杯个人赛，MIPS32，59MHz经典五级流水线架构，易于初学者阅读（计算机组成原理，自己动手写CPU）

53 (+2%)
mit
Last 12-months (new repositories)
no newly created repositories trending in the last 12 months
Last 12-months (absolute gain)
sudhamshu091
sudhamshu091/32-Verilog-Mini-Projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and...

587 (+219)
snbk001
snbk001/Verilog-Design-Examples

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion,...

95 (+60)
Gowtham1729
Gowtham1729/Image-Processing

Image Processing Toolbox in Verilog using Basys3 FPGA

183 (+53)
apache-2.0
michaelehab
michaelehab/AES-Verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

81 (+45)
zslwyuan
zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clo...

125 (+41)
gpl-3.0
Last 12-months (relative gain)
snbk001
snbk001/Verilog-Design-Examples

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion,...

95 (+171%)
Akashtailor-exe
Akashtailor-exe/30-days-of-verilog

30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

29 (+164%)
michaelehab
michaelehab/AES-Verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

81 (+125%)
xiazhuo
xiazhuo/nscc2022_personal

NSCSCC2022龙芯杯个人赛，MIPS32，59MHz经典五级流水线架构，易于初学者阅读（计算机组成原理，自己动手写CPU）

53 (+121%)
mit
prajwalgekkouga
prajwalgekkouga/AHB-to-APB-Bridge

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equiva...

49 (+81%)