Statistics for topic vhdl
RepositoryStats tracks 642,811 Github repositories, of these 97 are tagged with the vhdl topic. The most common primary language for repositories using this topic is VHDL (47). Other languages include: Python (15)
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Package manager and build abstraction tool for FPGA/ASIC development
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
Package manager and build abstraction tool for FPGA/ASIC development
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
Package manager and build abstraction tool for FPGA/ASIC development
Package manager and build abstraction tool for FPGA/ASIC development
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
IEEE 754 single and double precision floating point library in systemverilog and vhdl
VS Code based debugger for hardware designs in Amaranth or Verilog
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
An open-source HDL register code generator fast enough to run in real time.
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments