7 results found Sort:

427
2.7k
mit
102
A FPGA friendly 32 bit RISC-V CPU implementation
Created 2017-03-08
1,620 commits to master branch, last one 2 days ago
294
2.2k
bsd-3-clause
94
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Created 2018-08-19
370 commits to master branch, last one 8 hours ago
53
387
gpl-3.0
26
80186 compatible SystemVerilog CPU core and FPGA reference design
Created 2017-07-24
1,235 commits to master branch, last one 11 months ago
76
377
gpl-3.0
14
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC,包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
Created 2019-02-05
66 commits to master branch, last one about a year ago
29
340
unknown
25
A Forth CPU and System on a Chip, based on the J1, written in VHDL
Created 2013-04-19
725 commits to master branch, last one 11 months ago
:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and v...
Created 2021-01-02
689 commits to main branch, last one about a year ago
RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card
Created 2024-06-17
834 commits to main branch, last one a day ago