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VexRiscv SpinalHDL

435

2.7k

mit

103

A FPGA friendly 32 bit RISC-V CPU implementation

cpu soc fpga vhdl riscv verilog softcore spinalhdl

Created 2017-03-08

1,620 commits to master branch, last one about a month ago

USTC-RVSoC WangXuan95

77

395

gpl-3.0

13

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

cpu rtl soc fpga riscv rv32i risc-v verilog softcore systemverilog

Created 2019-02-05

66 commits to master branch, last one about a year ago

80x86 jamieiles

54

389

gpl-3.0

25

80186 compatible SystemVerilog CPU core and FPGA reference design

x86 fpga 80186 softcore systemverilog

Created 2017-07-24

1,235 commits to master branch, last one about a year ago

forth-cpu howerj

29

343

unknown

24

A Forth CPU and System on a Chip, based on the J1, written in VHDL

c cpu fpga vhdl forth softcore processor simulator target-board

Created 2013-04-19

725 commits to master branch, last one about a year ago

microrv32 agra-uni-bremen

6

45

mit

11

SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype

cpu rtl soc fpga vhdl riscv risc-v verilog softcore spinalhdl

Created 2021-05-17

32 commits to master branch, last one 5 months ago

tree-core-cpu microdynamics-cpu

3

38

gpl-3.0

5

:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and v...

cpu rtl riscv scala chisel softcore processor rt-thread verilator

Created 2021-01-02

689 commits to main branch, last one about a year ago

tang-nano-9k--riscv--cache-psram calint

1

28

unknown

2

RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card

rv32i risc-v softcore tang-nano-9k systemverilog

Created 2024-06-17

898 commits to main branch, last one 4 days ago