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VexRiscv SpinalHDL

421

2.5k

mit

102

A FPGA friendly 32 bit RISC-V CPU implementation

cpu soc fpga vhdl riscv verilog softcore spinalhdl

Created 2017-03-08

1,614 commits to master branch, last one about a month ago

darkriscv darklife

290

2.1k

bsd-3-clause

94

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

cpu rtl core fpga riscv rv32e rv32i risc-v verilog softcore processor processor-design

Created 2018-08-19

343 commits to master branch, last one about a month ago

80x86 jamieiles

51

383

gpl-3.0

26

80186 compatible SystemVerilog CPU core and FPGA reference design

x86 fpga 80186 softcore systemverilog

Created 2017-07-24

1,235 commits to master branch, last one 9 months ago

USTC-RVSoC WangXuan95

75

366

gpl-3.0

14

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

cpu rtl soc fpga riscv rv32i risc-v verilog softcore systemverilog

Created 2019-02-05

66 commits to master branch, last one about a year ago

forth-cpu howerj

29

334

unknown

24

A Forth CPU and System on a Chip, based on the J1, written in VHDL

c cpu fpga vhdl forth softcore processor simulator target-board

Created 2013-04-19

725 commits to master branch, last one 9 months ago

tree-core-cpu microdynamics-cpu

3

36

gpl-3.0

6

:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and v...

cpu rtl riscv scala chisel softcore processor rt-thread verilator

Created 2021-01-02

689 commits to main branch, last one about a year ago