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384

2.3k

mit

A FPGA friendly 32 bit RISC-V CPU implementation

cpu soc fpga vhdl riscv verilog softcore spinalhdl

Created 2017-03-08

1,589 commits to master branch, last one 2 months ago

270

1.9k

bsd-3-clause

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

cpu rtl core fpga riscv rv32e rv32i risc-v verilog softcore processor processor-design

Created 2018-08-19

282 commits to master branch, last one 7 days ago

365

gpl-3.0

80186 compatible SystemVerilog CPU core and FPGA reference design

x86 fpga 80186 softcore systemverilog

Created 2017-07-24

1,235 commits to master branch, last one 2 months ago

324

gpl-3.0

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

cpu rtl soc fpga riscv rv32i risc-v verilog softcore systemverilog

Created 2019-02-05

66 commits to master branch, last one 8 months ago

322

unknown

A Forth CPU and System on a Chip, based on the J1, written in VHDL

c cpu fpga vhdl forth softcore processor simulator target-board

Created 2013-04-19

725 commits to master branch, last one 2 months ago