WangXuan95 / USTC-RVSoC

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Date Created 2019-02-05 (5 years ago)

Commits 66 (last one about a year ago)

Stargazers 357 (1 this week)

Watchers 14 (0 this week)

Forks 75

License gpl-3.0

Ranking

RepositoryStats indexes 585,332 repositories, of these WangXuan95/USTC-RVSoC is ranked #116,561 (80th percentile) for total stargazers, and #155,085 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #26/173.

WangXuan95/USTC-RVSoC is also tagged with popular topics, for these it's ranked: fpga (#90/478), cpu (#88/285), verilog (#66/282), risc-v (#62/263), riscv (#53/166)

Other Information

WangXuan95/USTC-RVSoC has 2 open pull requests on Github, 1 pull request has been merged over the lifetime of the repository.

Github issues are enabled, there are 4 open issues and 4 closed issues.

Homepage URL: https://gitee.com/wangxuan95/USTC-RVSoC

All Topics

cpu rtl soc fpga riscv rv32i risc-v verilog softcore systemverilog

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

8 commits on the default branch (master) since jan '22

Yearly Commits

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Issue History

Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-11-20 @ 03:55pm, id: 169208857 / R_kgDOChXsGQ