Statistics for topic verilog
RepositoryStats tracks 579,129 Github repositories, of these 279 are tagged with the verilog topic. The most common primary language for repositories using this topic is Verilog (137). Other languages include: Python (22), C++ (21), SystemVerilog (20), C (14)
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Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product ...
合肥工业大学合肥校区（HFUT）计算机科学与技术专业（CS）。本仓库存有大一至大三的实验+课设及其源码，有疑问可以邮箱联系（回复时间不一定）。欢迎Star，会不定时更新
This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design
This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product ...
合肥工业大学合肥校区（HFUT）计算机科学与技术专业（CS）。本仓库存有大一至大三的实验+课设及其源码，有疑问可以邮箱联系（回复时间不一定）。欢迎Star，会不定时更新
This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design
This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
Verilator open-source SystemVerilog simulator and lint system
hardware design of universal NPU(CNN accelerator) for various convolution neural network
This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design
合肥工业大学合肥校区（HFUT）计算机科学与技术专业（CS）。本仓库存有大一至大三的实验+课设及其源码，有疑问可以邮箱联系（回复时间不一定）。欢迎Star，会不定时更新
Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)
Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
合肥工业大学合肥校区（HFUT）计算机科学与技术专业（CS）。本仓库存有大一至大三的实验+课设及其源码，有疑问可以邮箱联系（回复时间不一定）。欢迎Star，会不定时更新
Verilator open-source SystemVerilog simulator and lint system
Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
A configurable and approachable tool for FPGA debugging and rapid prototyping.
hardware design of universal NPU(CNN accelerator) for various convolution neural network
A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA