Statistics for topic verilog
RepositoryStats tracks 584,797 Github repositories, of these 282 are tagged with the verilog topic. The most common primary language for repositories using this topic is Verilog (137). Other languages include: Python (23), C++ (21), SystemVerilog (20), C (14)
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OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。
The next generation of OpenLane, rewritten from scratch with a modular architecture
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Verilator open-source SystemVerilog simulator and lint system
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design
合肥工业大学合肥校区（HFUT）计算机科学与技术专业（CS）。本仓库存有大一至大三的实验+课设及其源码，有疑问可以邮箱联系（回复时间不一定）。欢迎Star，会不定时更新
Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
Verilator open-source SystemVerilog simulator and lint system
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
hardware design of universal NPU(CNN accelerator) for various convolution neural network
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...
合肥工业大学合肥校区（HFUT）计算机科学与技术专业（CS）。本仓库存有大一至大三的实验+课设及其源码，有疑问可以邮箱联系（回复时间不一定）。欢迎Star，会不定时更新
This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design
Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
合肥工业大学合肥校区（HFUT）计算机科学与技术专业（CS）。本仓库存有大一至大三的实验+课设及其源码，有疑问可以邮箱联系（回复时间不一定）。欢迎Star，会不定时更新
Verilator open-source SystemVerilog simulator and lint system
Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
A configurable and approachable tool for FPGA debugging and rapid prototyping.
hardware design of universal NPU(CNN accelerator) for various convolution neural network
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...
