Statistics for topic verilog
RepositoryStats tracks 595,856 Github repositories, of these 289 are tagged with the verilog topic. The most common primary language for repositories using this topic is Verilog (143). Other languages include: Python (23), C++ (21), SystemVerilog (19), C (13)
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OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.
合肥工业大学合肥校区（HFUT）计算机科学与技术专业（CS）。本仓库存有大一至大三的实验+课设及其源码，有疑问可以邮箱联系（回复时间不一定）。欢迎Star，会不定时更新
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.
hardware design of universal NPU(CNN accelerator) for various convolution neural network
合肥工业大学合肥校区（HFUT）计算机科学与技术专业（CS）。本仓库存有大一至大三的实验+课设及其源码，有疑问可以邮箱联系（回复时间不一定）。欢迎Star，会不定时更新
Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
Verilator open-source SystemVerilog simulator and lint system
Verilog code to replace the Commodore SDMAC found in the A3000
Verilog implementation of PAL, NTSC and SECAM color encoding
The next generation of OpenLane, rewritten from scratch with a modular architecture
合肥工业大学合肥校区（HFUT）计算机科学与技术专业（CS）。本仓库存有大一至大三的实验+课设及其源码，有疑问可以邮箱联系（回复时间不一定）。欢迎Star，会不定时更新
Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
合肥工业大学合肥校区（HFUT）计算机科学与技术专业（CS）。本仓库存有大一至大三的实验+课设及其源码，有疑问可以邮箱联系（回复时间不一定）。欢迎Star，会不定时更新
Verilator open-source SystemVerilog simulator and lint system
Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
A configurable and approachable tool for FPGA debugging and rapid prototyping.
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...
hardware design of universal NPU(CNN accelerator) for various convolution neural network
