Statistics for topic verilog

RepositoryStats tracks 518,986 Github repositories, of these 247 are tagged with the verilog topic. The most common primary language for repositories using this topic is Verilog (121). Other languages include: Python (23), C++ (19), SystemVerilog (18), C (13)

Stargazers over time for topic verilog

Most starred repositories for topic verilog (view more)

logisim-evolution logisim-evolution

574

4.4k

gpl-3.0

63

Digital logic design tool and simulator

fpga vhdl logic circuit logisim verilog circuits education simulator digital-logic timing-diagram digital-circuit digital-circuits logisim-evolution digital-logic-design

Created 2014-09-19

4,936 commits to main branch, last one a day ago

chisel chipsalliance

573

3.7k

apache-2.0

148

Chisel: A Modern Hardware Design Language

rtl scala chisel firrtl chisel3 verilog chip-generator

Created 2015-04-27

5,900 commits to main branch, last one 7 days ago

openwifi open-sdr

608

3.6k

agpl-3.0

130

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Created 2019-11-08

812 commits to master branch, last one about a month ago

FPGA LeiWang1999

616

3.4k

unknown

58

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga pynq vivado xilinx verilog

Created 2020-06-26

85 commits to master branch, last one 2 years ago

VexRiscv SpinalHDL

382

2.3k

mit

98

A FPGA friendly 32 bit RISC-V CPU implementation

cpu soc fpga vhdl riscv verilog softcore spinalhdl

Created 2017-03-08

1,589 commits to master branch, last one about a month ago

verilator verilator

535

2.2k

lgpl-3.0

74

Verilator open-source SystemVerilog simulator and lint system

cpp rtl systemc verilog compilers verilator system-verilog verilog-simulator

Created 2019-06-13

6,947 commits to master branch, last one 3 days ago

Trending repositories for topic verilog (view more)