Statistics for topic verilog

RepositoryStats tracks 638,594 Github repositories, of these 313 are tagged with the verilog topic. The most common primary language for repositories using this topic is Verilog (153). Other languages include: Python (26), C++ (22), SystemVerilog (21), VHDL (13), C (12)

Stargazers over time for topic verilog

Most starred repositories for topic verilog (view more)

logisim-evolution logisim-evolution

709

5.6k

gpl-3.0

71

Digital logic design tool and simulator

fpga vhdl logic circuit logisim verilog circuits education simulator digital-logic timing-diagram digital-circuit digital-circuits logisim-evolution digital-logic-design

Created 2014-09-19

5,256 commits to main branch, last one 2 days ago

FPGA LeiWang1999

725

4.5k

unknown

67

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga pynq vivado xilinx verilog

Created 2020-06-26

85 commits to master branch, last one 2 years ago

chisel chipsalliance

621

4.2k

apache-2.0

151

Chisel: A Modern Hardware Design Language

rtl scala chisel firrtl chisel3 verilog chip-generator

Created 2015-04-27

6,650 commits to main branch, last one a day ago

openwifi open-sdr

693

4.1k

agpl-3.0

131

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Created 2019-11-08

850 commits to master branch, last one 22 days ago

verilator verilator

649

2.8k

lgpl-3.0

73

Verilator open-source SystemVerilog simulator and lint system

cpp rtl systemc verilog compilers verilator system-verilog verilog-simulator

Created 2019-06-13

7,800 commits to master branch, last one 18 hours ago

VexRiscv SpinalHDL

441

2.7k

mit

103

A FPGA friendly 32 bit RISC-V CPU implementation

cpu soc fpga vhdl riscv verilog softcore spinalhdl

Created 2017-03-08

1,620 commits to master branch, last one about a month ago

Trending repositories for topic verilog (view more)