Trending repositories for topic verilog

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

Digital logic design tool and simulator

Veryl: A Modern Hardware Description Language

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

Verilator open-source SystemVerilog simulator and lint system

The Ultra-Low Power RISC-V Core

Code generation tool for control and status registers

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed...

Must-have verilog systemverilog modules

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

The next generation of OpenLane, rewritten from scratch with a modular architecture

Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.

A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.

High throughput JPEG decoder in Verilog for FPGA

An FPGA-based FT232H/FT600 chip controller for rapid data transmission via USB. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product ...

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

Veryl: A Modern Hardware Description Language

Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.

A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

The next generation of OpenLane, rewritten from scratch with a modular architecture

Code generation tool for control and status registers

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed...

High throughput JPEG decoder in Verilog for FPGA

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

The Ultra-Low Power RISC-V Core

An FPGA-based FT232H/FT600 chip controller for rapid data transmission via USB. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product ...

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and...

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

The OpenPiton Platform

HDLBits website practices & solutions

Must-have verilog systemverilog modules

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

Digital logic design tool and simulator

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

The Ultra-Low Power RISC-V Core

Verilator open-source SystemVerilog simulator and lint system

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

The next generation of OpenLane, rewritten from scratch with a modular architecture

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed...

RISC-V CPU Core (RV32IM)

Chisel: A Modern Hardware Design Language

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and...

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A FPGA friendly 32 bit RISC-V CPU implementation

Must-have verilog systemverilog modules

Opensource DDR3 Controller

Code generation tool for control and status registers

The next generation of OpenLane, rewritten from scratch with a modular architecture

A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated by ChatGPT-4 with advanced optimizations.

hardware design of universal NPU(CNN accelerator) for various convolution neural network

This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.

VHDL Guide

Opensource DDR3 Controller

A modern and open-source cross-platform software for chips reverse engineering.

Verilog package manager written in Rust

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

合肥工业大学合肥校区（HFUT）计算机科学与技术专业（CS）。本仓库存有大一至大三的实验+课设及其源码，有疑问可以邮箱联系（回复时间不一定）。欢迎Star，会不定时更新

Code generation tool for control and status registers

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed...

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product ...

Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)

My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu

A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.

Control and Status Register map generator for HDL projects

An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). 基于FPGA的GZIP压缩器。输入原始数据，输出标准的GZIP格式，即常见的 .gz / .tar.gz 文件的格式。

High throughput JPEG decoder in Verilog for FPGA

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

Digital logic design tool and simulator

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilator open-source SystemVerilog simulator and lint system

Chisel: A Modern Hardware Design Language

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

The Ultra-Low Power RISC-V Core

RISC-V CPU Core (RV32IM)

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

A FPGA friendly 32 bit RISC-V CPU implementation

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Opensource DDR3 Controller

Scala based HDL

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

SERV - The SErial RISC-V CPU

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Must-have verilog systemverilog modules

SystemVerilog compiler and language services

Atari 2600 Open-source System-on-Chip (SoC)

hardware design of universal NPU(CNN accelerator) for various convolution neural network

合肥工业大学合肥校区（HFUT）计算机科学与技术专业（CS）。本仓库存有大一至大三的实验+课设及其源码，有疑问可以邮箱联系（回复时间不一定）。欢迎Star，会不定时更新

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...

Opensource DDR3 Controller

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum

A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated by ChatGPT-4 with advanced optimizations.

Verilog package manager written in Rust

High-speed full CRYSTALS-DILITHIUM implementation on FPGA: Keygen, Sign, Verify.

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA

This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design

Control and status register code generator toolchain

Delta Sigma DAC FPGA

The next generation of OpenLane, rewritten from scratch with a modular architecture

My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu

Simple 8-bit UART realization on Verilog HDL.

Structural Netlist API (and more) for EDA post synthesis flow development

A simple RISC-V CPU written in Verilog.

Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

Verilog package manager written in Rust

合肥工业大学合肥校区（HFUT）计算机科学与技术专业（CS）。本仓库存有大一至大三的实验+课设及其源码，有疑问可以邮箱联系（回复时间不一定）。欢迎Star，会不定时更新

Sol-1: A CPU/Computer System made from 74 series logic.

Playground for VGA projects on Tiny Tapeout

Apple II FPGA Co-Processor

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...

VS Code based debugger for hardware designs in Amaranth or Verilog

Atari 2600 Open-source System-on-Chip (SoC)

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

Digital logic design tool and simulator

Verilator open-source SystemVerilog simulator and lint system

Chisel: A Modern Hardware Design Language

Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

A FPGA friendly 32 bit RISC-V CPU implementation

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

The Ultra-Low Power RISC-V Core

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Must-have verilog systemverilog modules

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

RISC-V Linux SoC, marchID: 0x2b

Veryl: A Modern Hardware Description Language

SERV - The SErial RISC-V CPU

RISC-V CPU Core (RV32IM)

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed...

A configurable and approachable tool for FPGA debugging and rapid prototyping.

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...

hardware design of universal NPU(CNN accelerator) for various convolution neural network

Opensource DDR3 Controller

Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)

A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA

This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design

A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated by ChatGPT-4 with advanced optimizations.

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion,...

Package manager and build tool for HDLs

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

The next generation of OpenLane, rewritten from scratch with a modular architecture

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward Error Correction coders and decoders Hamming code, Golay code ...

Delta Sigma DAC FPGA

Sol-1: A CPU/Computer System made from 74 series logic.

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product ...

Veryl: A Modern Hardware Description Language

30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!