Trending repositories for topic verilog
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
PlatformIO IDE for VSCode: The next generation integrated development environment for IoT
Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and...
Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database
PlatformIO IDE for VSCode: The next generation integrated development environment for IoT
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and...
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
Verilator open-source SystemVerilog simulator and lint system
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database
An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。
Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G ...
hardware design of universal NPU(CNN accelerator) for various convolution neural network
Learn how to build our own RV32I core and use it on FPGA.
Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward Error Correction coders and decoders Hamming code, Golay code ...
The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
A novel architectural design for stitching video streams in real-time on an FPGA.
Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database
An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器，可实现视频压缩。
Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Verilator open-source SystemVerilog simulator and lint system
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and...
The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com
🦀 No nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl
Learn how to build our own RV32I core and use it on FPGA.
Leaky Integrate and Fire (LIF) model implementation for FPGA
IC implementation of Systolic Array for TPU
This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。
Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images
A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA
Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward Error Correction coders and decoders Hamming code, Golay code ...
RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.
合肥工业大学合肥校区（HFUT）计算机科学与技术专业（CS）。本仓库存有大一至大三的实验+课设及其源码，有疑问可以邮箱联系（回复时间不一定）。欢迎Star，会不定时更新
An FPGA-based MII to RMII & SMII converter to connect 100M ethernet PHY chip such as LAN8720 or KSZ8041TLI-S. 基于FPGA的MII转RMII和MII转SMII，用来连接LAN8720、KSZ8041TLI-S等百兆以太网PHY芯片。
A huge collection of VHDL/Verilog open-source IP cores scraped from the web
The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...
🦀 No nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl
VS Code based debugger for hardware designs in Amaranth or Verilog
Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.
A tool for compression of lookup tables and generation of their hardware files in Verilog for RTL designs
Verilator open-source SystemVerilog simulator and lint system
Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed...
Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
Learn how to build our own RV32I core and use it on FPGA.
合肥工业大学合肥校区（HFUT）计算机科学与技术专业（CS）。本仓库存有大一至大三的实验+课设及其源码，有疑问可以邮箱联系（回复时间不一定）。欢迎Star，会不定时更新
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...
Verilog implementation of PAL, NTSC and SECAM color encoding
hardware design of universal NPU(CNN accelerator) for various convolution neural network
RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.
This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design
Systolic array based simple TPU for CNN on PYNQ-Z2
RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
