AhmedAalaaa / 32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm

This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design

AhmedAalaaa
AhmedAalaaa
Date Created 2021-07-30 (3 years ago)
Commits 30 (last one about a year ago)
Stargazers 44 (0 this week)
Watchers 1 (0 this week)
Forks 7
License unknown
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RepositoryStats indexes 584,353 repositories, of these AhmedAalaaa/32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm is ranked #493,318 (16th percentile) for total stargazers, and #535,930 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #438/535.

AhmedAalaaa/32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm is also tagged with popular topics, for these it's ranked: cpp (#3,020/3423),  fpga (#424/478),  matlab (#314/351),  verilog (#250/282)

Other Information

AhmedAalaaa/32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm has Github issues enabled, there is 1 open issue and 0 closed issues.

All Topics
cpp tcl fpga matlab verilog

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16 commits on the default branch (main) since jan '22

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The primary language is Verilog but there's also others...

updated: 2024-11-19 @ 08:56am, id: 391096744 / R_kgDOF0-pqA