Statistics for topic fpga
RepositoryStats tracks 579,129 Github repositories, of these 474 are tagged with the fpga topic. The most common primary language for repositories using this topic is Verilog (139). Other languages include: Python (58), C++ (49), VHDL (46), C (43), SystemVerilog (32), Scala (14)
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John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product ...
This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs
John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product ...
This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs
John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs
A Python library for converting images into FPGA-displayable pixel art.
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.
Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application
This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs
A Python library for converting images into FPGA-displayable pixel art.
A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.
Commodore C64 core for the Tang Nano 20K Primer 25K Mega 60k and Mega 138K Pro FPGA
A configurable and approachable tool for FPGA debugging and rapid prototyping.
