28 results found Sort:

LeiWang1999
FPGA LeiWang1999
628
3.5k
unknown
60
帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
fpga pynq vivado xilinx verilog
Created 2020-06-26
85 commits to master branch, last one 2 years ago
fastmachinelearning
hls4ml fastmachinelearning
385
1.2k
apache-2.0
55
Machine learning on FPGAs using HLS
hls fpga onnx keras python vivado pytorch intel-hls vivado-hls neural-network machine-learning
Created 2017-10-25
2,012 commits to main branch, last one 19 hours ago
hdl-util
hdmi hdl-util
111
1.0k
other
43
Send video/audio over HDMI on an FPGA
dvi fpga hdmi audio intel video altera vivado xilinx hdlmake quartus systemverilog
Created 2019-08-17
306 commits to master branch, last one 4 months ago
eugene-tarassov
vivado-risc-v eugene-tarassov
180
774
unknown
33
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
boom fpga kc705 linux riscv vc707 risc-v vivado xilinx arty-a7 genesys2 rocketchip nexys-video
Created 2020-02-15
417 commits to master branch, last one 6 days ago
f4pga
prjxray f4pga
150
748
isc
60
Documenting the Xilinx 7-series bit-stream format.
fpga artix tools artix7 fuzzer vivado xilinx kintex7 bitstream symbiflow toolchain xilinx-fpga
Created 2017-12-16
3,874 commits to master branch, last one 6 days ago
olofk
edalize olofk
183
602
bsd-2-clause
34
An abstraction library for interfacing EDA tools
eda fpga ghdl vhdl fossi yosys altera vivado xilinx lattice verilog icestorm modelsim spyglass synthesis verilator simulation riviera-pro systemverilog icarus-verilog
Created 2018-05-09
523 commits to main branch, last one about a month ago
pavel-demin
red-pitaya-notes pavel-demin
200
326
mit
52
Notes on the Red Pitaya Open Source Instrument
dsp mca nmr sdr tcl vna fpga wspr zynq linux radio vitis vivado xilinx verilog redpitaya red-pitaya
Created 2014-12-23
2,907 commits to master branch, last one 29 days ago
changwoolee
lenet5_hls changwoolee
91
291
mit
12
FPGA Accelerator for CNN using Vivado HLS
cnn hls sdx lenet sdsoc vivado accelerator high-level-synthesis
Created 2017-05-25
65 commits to master branch, last one 2 years ago
mshr-h
vscode-verilog-hdl-support mshr-h
76
283
mit
9
HDL support for VS Code
svls ctags vivado vscode verilog iverilog modelsim verilator verilog-hdl hacktoberfest systemverilog icarus-verilog systemverilog-support bluespec-systemverilog language-server-client
Created 2015-12-10
536 commits to main branch, last one 20 days ago
Xilinx
RapidWright Xilinx
104
274
other
26
Build Customized FPGA Implementations for Vivado
fpga vivado xilinx rapidwright
Created 2017-08-29
1,744 commits to master branch, last one a day ago
ichi4096
vivado-on-silicon-mac ichi4096
25
213
cc0-1.0
8
Installs Vivado on M1/M2 macs
arm fpga arm64 macos docker vivado aarch64 vivado-installer
Created 2023-04-06
42 commits to main branch, last one 9 months ago
Gowtham1729
Image-Processing Gowtham1729
37
167
apache-2.0
4
Image Processing Toolbox in Verilog using Basys3 FPGA
coe ram fpga vhdl basys hsync pixel basys3 python vivado python3 verilog basys-board basys3-fpga convolution motion-blur verilog-hdl digital-systems verilog-project image-processing
Created 2018-12-04
44 commits to master branch, last one 9 months ago
UCLA-VAST
RapidStream UCLA-VAST
17
112
mit
6
[FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
hls fpga vivado routing dataflow parallel placement
Created 2020-12-13
798 commits to main branch, last one about a year ago
ilaydayaman
CNN_for_SLR ilaydayaman
30
84
bsd-2-clause
5
A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
cnn slr fpga vivado verilog
Created 2018-06-30
18 commits to master branch, last one 6 months ago
tomas-fryza
vhdl-course tomas-fryza
230
81
mit
9
VHDL course at Brno University of Technology
fpga vhdl vivado nexys-a7 teroshdl brno-university-of-technology
Created 2020-01-17
1,502 commits to master branch, last one 22 days ago
WangXuan95
Zynq-Tutorial WangXuan95
14
79
gpl-3.0
4
使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例
zynq vivado soc-fpga zedboard petalinux zynq-7020 block-design
Created 2020-10-11
5 commits to main branch, last one 9 months ago
PyFPGA
pyfpga PyFPGA
7
78
gpl-3.0
4
A Python package to use FPGA development tools programmatically.
amd ise tcl fpga ghdl actel intel yosys altera libero python vivado xilinx lattice nextpnr quartus trellis icestorm microchip microsemi
Created 2021-02-10
502 commits to main branch, last one 2 years ago
hdl-modules
hdl-modules hdl-modules
9
78
bsd-3-clause
4
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
ip amd axi cdc eda rtl asic fifo fpga vhdl intel altera efinix vivado xilinx axi-lite hardware microsemi asynchronous-fifo clock-domain-crossing
Created 2023-11-30
394 commits to main branch, last one 4 days ago
lauchinyuan
FPGA_QPSK-modem lauchinyuan
19
76
unknown
2
A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA
fpga qpsk matlab vivado verilog
Created 2023-04-15
45 commits to master branch, last one 7 months ago
hukenovs
intfftk hukenovs
25
73
gpl-3.0
7
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
dsp fft fpga vhdl altera vivado xilinx radix-2 verilog cooley-tukey-fft fast-convolutions integer-arithmetic route-optimization fast-fourier-transform digital-signal-processing
Created 2018-08-17
87 commits to master branch, last one about a year ago
KeitetsuWorks
EBAZ4205 KeitetsuWorks
25
71
mit
9
Vivado and PetaLinux projects for Zynq EBAZ4205 Board
fpga zynq vivado xilinx ebaz4205 petalinux
Created 2021-04-03
20 commits to master branch, last one 2 years ago
f4pga
prjuray f4pga
13
69
apache-2.0
19
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
fpga fuzzer vivado xilinx bitstream symbiflow ultrascale xilinx-fpga ultrascale-plus
Created 2020-07-15
28 commits to master branch, last one 2 years ago
suoglu
Fixed-Floating-Point-Adder-Multiplier suoglu
12
58
other
5
16-bit Adder Multiplier hardware on Digilent Basys 3
fpga adder vivado verilog binary16 hardware multiplier fixed-point floating-point
Created 2017-06-06
105 commits to master branch, last one 11 months ago
OVGN
OpenHBMC OVGN
11
53
apache-2.0
5
Open-source high performance AXI4-based HyperRAM memory controller
fpga vivado xilinx
Created 2020-09-20
26 commits to master branch, last one about a year ago
li3tuo4
rc-fpga-zcu li3tuo4
15
51
other
3
Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
risc-v vivado zcu102 zynqmp fpga-board linux-boot rocket-chip
Created 2019-01-08
272 commits to publish branch, last one about a year ago
FDUCSLG
ICS-2021Spring-FDU FDUCSLG
19
44
gpl-3.0
3
Introduction to Computer Systems (II), Spring 2021
fpga mips nscscc vivado verilator systemverilog
Created 2021-02-27
45 commits to master branch, last one 2 years ago
MJoergen
HyperRAM MJoergen
10
44
mit
7
Portable HyperRAM controller
fpga vhdl artix intel altera avalon questa vivado xilinx lattice quartus hyperram modelsim questasim
Created 2022-01-07
163 commits to main branch, last one 2 days ago
mwrnd
innova2_flex_xcku15p_notes mwrnd
6
39
bsd-2-clause
5
Nvidia/Mellanox Innova-2 Flex Open Programmable SmartNIC Setup and Usage Notes for XCKU15P FPGA Development
fpga urjtag vivado 01pg974 innova2 xcku15p mt27808a0 mt28808a0 nv303212a 4xc7a16683 mnv303212a innova-2-flex mnv303212a-adlt mnv303611a-edlt innova2-8gb-adlt kintex-ultrascale
Created 2022-06-19
132 commits to main branch, last one 2 months ago