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帮助大家进行FPGA的入门,分享FPGA相关的优秀文章,优秀项目
Created
2020-06-26
85 commits to master branch, last one 2 years ago
Machine learning on FPGAs using HLS
Created
2017-10-25
1,997 commits to main branch, last one 2 days ago
Send video/audio over HDMI on an FPGA
Created
2019-08-17
306 commits to master branch, last one 4 months ago
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
Created
2020-02-15
416 commits to master branch, last one 20 hours ago
Documenting the Xilinx 7-series bit-stream format.
Created
2017-12-16
3,869 commits to master branch, last one 4 days ago
An abstraction library for interfacing EDA tools
Created
2018-05-09
523 commits to main branch, last one 27 days ago
Notes on the Red Pitaya Open Source Instrument
Created
2014-12-23
2,907 commits to master branch, last one 14 days ago
FPGA Accelerator for CNN using Vivado HLS
Created
2017-05-25
65 commits to master branch, last one 2 years ago
HDL support for VS Code
Created
2015-12-10
536 commits to main branch, last one 4 days ago
Build Customized FPGA Implementations for Vivado
Created
2017-08-29
1,737 commits to master branch, last one 23 hours ago
Installs Vivado on M1/M2 macs
Created
2023-04-06
42 commits to main branch, last one 8 months ago
Image Processing Toolbox in Verilog using Basys3 FPGA
Created
2018-12-04
44 commits to master branch, last one 8 months ago
[FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
Created
2020-12-13
798 commits to main branch, last one about a year ago
A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
Created
2018-06-30
18 commits to master branch, last one 6 months ago
VHDL course at Brno University of Technology
Created
2020-01-17
1,502 commits to master branch, last one 7 days ago
A Python package to use FPGA development tools programmatically.
Created
2021-02-10
502 commits to main branch, last one 2 years ago
使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例
Created
2020-10-11
5 commits to main branch, last one 9 months ago
A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA
Created
2023-04-15
45 commits to master branch, last one 6 months ago
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
Created
2018-08-17
87 commits to master branch, last one about a year ago
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Created
2023-11-30
393 commits to main branch, last one 6 days ago
Vivado and PetaLinux projects for Zynq EBAZ4205 Board
Created
2021-04-03
20 commits to master branch, last one 2 years ago
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
Created
2020-07-15
28 commits to master branch, last one 2 years ago
16-bit Adder Multiplier hardware on Digilent Basys 3
Created
2017-06-06
105 commits to master branch, last one 10 months ago
Open-source high performance AXI4-based HyperRAM memory controller
Created
2020-09-20
26 commits to master branch, last one about a year ago
Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
Created
2019-01-08
272 commits to publish branch, last one about a year ago
Portable HyperRAM controller
Created
2022-01-07
162 commits to main branch, last one 22 days ago
Introduction to Computer Systems (II), Spring 2021
Created
2021-02-27
45 commits to master branch, last one 2 years ago
Nvidia/Mellanox Innova-2 Flex Open Programmable SmartNIC Setup and Usage Notes for XCKU15P FPGA Development
Created
2022-06-19
132 commits to main branch, last one 2 months ago