4 results found Sort:

suoto
hdl_checker suoto
26
207
gpl-3.0
16
Repurposing existing HDL tools to help writing better code
hdl vim ghdl vhdl python xilinx verilog vim-ale coc-nvim modelsim emacs-lsp questasim lsp-server hdl-checker mentor-msim systemverilog xilinx-vivado syntax-checker language-server vivado-simulator
Created 2016-01-23
390 commits to master branch, last one 3 years ago
Paebbels
JSON-for-VHDL Paebbels
17
79
other
13
A JSON library implemented in VHDL.
fpga ghdl json vhdl parser xilinx lattice modelsim questasim synthesis fileformat simulation
Created 2015-09-01
61 commits to master branch, last one 2 years ago
MJoergen
HyperRAM MJoergen
14
54
mit
6
Portable HyperRAM controller
fpga vhdl artix intel altera avalon questa vivado xilinx lattice quartus hyperram modelsim questasim
Created 2022-01-07
164 commits to main_old branch, last one 6 months ago
Ghonimo
Pre_Silicon-AHB-to_APB-Verification Ghonimo
6
25
mit
1
Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
uvm vip ahb2apb questasim testbench simulation verification semiconductor systemverilog digital-design uvm-verification verification-methodologies
Created 2023-08-03
14 commits to main branch, last one about a year ago