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A modern hardware definition language and toolchain based on Python
Created
2020-01-27
1,741 commits to main branch, last one 8 days ago
🧩 Monibuca is a Modularized, Extensible framework for building Streaming Server
Created
2020-01-23
358 commits to v4 branch, last one 9 days ago
HDL libraries and projects
Created
2014-02-20
6,618 commits to main branch, last one 5 days ago
A repository of gate-level simulators and tools for the original Game Boy.
Created
2019-04-21
4,163 commits to master branch, last one 4 months ago
Hardware Description Languages
Created
2017-04-12
165 commits to master branch, last one about a month ago
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
Created
2018-12-08
829 commits to master branch, last one 2 years ago
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。
Created
2022-02-20
19 commits to main branch, last one 9 months ago
bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
Created
2020-12-31
14 commits to main branch, last one 2 months ago
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
Created
2017-02-22
2,389 commits to master branch, last one 6 months ago
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
Created
2021-09-22
254 commits to main branch, last one 17 hours ago
Open source machine learning accelerators
Created
2022-02-26
466 commits to main branch, last one about a year ago
VeloView performs real-time visualization and easy processing of live captured 3D LiDAR data from Velodyne sensors (Alpha Prime™, Puck™, Ultra Puck™, Puck Hi-Res™, Alpha Puck™, Puck LITE™, HDL-32, HDL...
Created
2015-01-15
2,422 commits to master branch, last one 2 years ago
PlutoSDR Firmware
Created
2016-11-02
157 commits to master branch, last one 4 months ago
A huge VHDL library for FPGA development
Created
2016-08-23
7,505 commits to master branch, last one 7 days ago
This is a repository containing solutions to the problem statements given in HDL Bits website.
Created
2019-06-07
71 commits to master branch, last one 2 years ago
Reviewing some online CS courses I took
Created
2020-06-10
922 commits to master branch, last one about a month ago
Test suite designed to check compliance with the SystemVerilog standard.
Created
2019-08-08
8,039 commits to master branch, last one 5 days ago
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Created
2017-11-16
5,217 commits to main branch, last one a day ago
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Created
2017-03-28
49 commits to master branch, last one 2 months ago
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
Created
2018-04-23
6,507 commits to master branch, last one 7 days ago
An HDL embedded in Rust.
This repository has been archived
(exclude archived)
Created
2019-12-22
217 commits to master branch, last one 7 months ago
Repurposing existing HDL tools to help writing better code
Created
2016-01-23
390 commits to master branch, last one 2 years ago
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
Created
2016-12-13
4,467 commits to main branch, last one 8 days ago
HDL symbol generator
Created
2017-01-26
38 commits to master branch, last one 6 years ago
A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog
Created
2022-12-30
624 commits to master branch, last one 10 months ago
Support files for participating in a Fomu workshop
Created
2019-08-16
661 commits to master branch, last one 3 months ago
A C++ to Verilog translation tool with some basic guarantees that your code will work.
Created
2019-11-25
1,732 commits to master branch, last one 25 days ago
Custom chips reverse-engineered from silicon
Created
2019-12-27
155 commits to master branch, last one 4 months ago
Revengineered ancient PDP-11 CPUs, originals and clones
Created
2018-11-24
96 commits to master branch, last one 6 months ago
HW Design: A Functional Approach
Created
2018-03-12
1,711 commits to master branch, last one 2 years ago