56 results found Sort:

amaranth-lang
amaranth amaranth-lang
176
1.6k
bsd-2-clause
46
A modern hardware definition language and toolchain based on Python
hdl fpga amaranth-hdl
Created 2020-01-27
1,798 commits to main branch, last one about a month ago
analogdevicesinc
hdl analogdevicesinc
1.5k
1.6k
other
159
HDL libraries and projects
hdl fpga verilog jesd204b hacktoberfest analog-devices
Created 2014-02-20
6,871 commits to main branch, last one 2 days ago
langhuihui
monibuca langhuihui
247
1.5k
mit
36
🧩 Monibuca is a Modularized, Extensible framework for building Streaming Server
ts flv hdl hls rtp rtmp rtsp webrtc websocket livestream mediaserver
Created 2020-01-23
368 commits to v4 branch, last one 8 days ago
aappleby
metroboy aappleby
36
1.1k
unknown
25
A repository of gate-level simulators and tools for the original Game Boy.
hdl gameboy verilog emulator simulator gameboy-emulator
Created 2019-04-21
4,166 commits to master branch, last one about a month ago
drom
awesome-hdl drom
97
979
unknown
62
Hardware Description Languages
hdl vhdl awesome verilog awesome-list hacktoberfest hardware-description-language
Created 2017-04-12
165 commits to master branch, last one 7 months ago
m-labs
nmigen m-labs
57
662
other
51
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
hdl fpga yosys nmigen
Created 2018-12-08
829 commits to master branch, last one 2 years ago
veryl-lang
veryl veryl-lang
27
550
other
13
Veryl: A Modern Hardware Description Language
hdl rtl rust verilog systemverilog
Created 2022-12-08
2,319 commits to master branch, last one 2 days ago
WangXuan95
BSV_Tutorial_cn WangXuan95
43
534
gpl-3.0
12
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
bsv hdl fpga verilog bluespec bluespec-systemverilog hardware-description-language
Created 2022-02-20
19 commits to main branch, last one about a year ago
Nuand
bladeRF-wiphy Nuand
50
397
gpl-2.0
24
bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
hdl rtl dsss ofdm vhdl 80211 bladerf ofdm-wireless-communications
Created 2020-12-31
14 commits to main branch, last one 8 months ago
pymtl
pymtl3 pymtl
48
390
bsd-3-clause
21
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
hdl rtl pymtl python verilog systemverilog open-source-eda hardware-generation cycle-level-modeling multi-level-modeling open-source-hardware
Created 2017-02-22
2,390 commits to master branch, last one 12 days ago
intel
rohd intel
68
377
bsd-3-clause
15
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
hdl rtl hardware framework simulator verification hardware-design hardware-verification
Created 2021-09-22
267 commits to main branch, last one 3 days ago
tensil-ai
tensil tensil-ai
29
361
other
10
Open source machine learning accelerators
hdl asic fpga scala silicon machine-learning artificial-intelligence
Created 2022-02-26
466 commits to main branch, last one 2 years ago
slaclab
surf slaclab
60
350
other
49
A huge VHDL library for FPGA development
hdl asic fpga vhdl python firmware
Created 2016-08-23
7,805 commits to main branch, last one 15 days ago
analogdevicesinc
plutosdr-fw analogdevicesinc
199
337
other
74
PlutoSDR Firmware
rf hdl iio sdr fpga linux plutosdr adalm-pluto plutosdr-fw transceiver plutosdr-firmware active-learning-module
Created 2016-11-02
158 commits to master branch, last one 2 months ago
viduraakalanka
HDL-Bits-Solutions viduraakalanka
91
335
unlicense
3
This is a repository containing solutions to the problem statements given in HDL Bits website.
hdl verilog
Created 2019-06-07
71 commits to master branch, last one 2 years ago
Kitware
VeloView Kitware
166
316
apache-2.0
41
VeloView performs real-time visualization and easy processing of live captured 3D LiDAR data from Velodyne sensors (Alpha Prime™, Puck™, Ultra Puck™, Puck Hi-Res™, Alpha Puck™, Puck LITE™, HDL-32, HDL...
hdl lidar velodyne sensor-data velodyne-sensor sensor-streaming lidar-measurements velodyne-hdl-sensors lidar-data-manipulation lidar-camera-calibration
Created 2015-01-15
2,422 commits to master branch, last one 3 years ago
chipsalliance
sv-tests chipsalliance
75
304
isc
19
Test suite designed to check compliance with the SystemVerilog standard.
hdl rtl verilog symbiflow systemverilog compliance-testing
Created 2019-08-08
8,962 commits to master branch, last one 19 hours ago
spamegg1
reviews spamegg1
18
300
gpl-3.0
16
Reviewing some online CS courses I took
c hdl java ruby logic scala smlnj kotlin python racket assembly databases algorithms javascript networking mathematics nand2tetris computer-graphics operating-systems programming-languages
Created 2020-06-10
936 commits to master branch, last one 2 months ago
dpretet
async_fifo dpretet
77
283
other
11
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
cdc hdl asic fifo fpga async verilog synthesis verilator fifo-cache fifo-queue asic-design verilog-hdl verification icarus-verilog cross-clock-domain
Created 2017-03-28
49 commits to master branch, last one 8 months ago
f4pga
f4pga-arch-defs f4pga
113
273
isc
25
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
hdl vpr fpga artix ice40 artix7 python sphinx kintex7 lattice verilog symbiflow synthesis toolchain primitives xilinx-fpga documentation verilog-simulator verilog-simulations architecture-definitions
Created 2017-11-16
5,223 commits to main branch, last one 3 months ago
masc-ucsc
livehd masc-ucsc
48
214
other
29
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
hdl asic fpga live lgraph synthesis simulation
Created 2018-04-23
6,528 commits to master branch, last one 3 months ago
catkira
open5G_phy catkira
33
197
agpl-3.0
14
A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog
5g hdl fpga 5g-nr verilog 5g-simulation
Created 2022-12-30
624 commits to master branch, last one about a year ago
kactus2
kactus2dev kactus2
35
196
gpl-2.0
24
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
eda hdl fpga mpsoc reuse design ip-xact hardware system-on-chip
Created 2016-12-13
4,523 commits to main branch, last one 18 days ago
yupferris
kaze yupferris
9
195
apache-2.0
14
An HDL embedded in Rust.
hdl rust digital-logic-design
This repository has been archived (exclude archived)
Created 2019-12-22
217 commits to master branch, last one about a year ago
suoto
hdl_checker suoto
23
195
gpl-3.0
17
Repurposing existing HDL tools to help writing better code
hdl vim ghdl vhdl python xilinx verilog vim-ale coc-nvim modelsim emacs-lsp questasim lsp-server hdl-checker mentor-msim systemverilog xilinx-vivado syntax-checker language-server vivado-simulator
Created 2016-01-23
390 commits to master branch, last one 2 years ago
kevinpt
symbolator kevinpt
49
186
mit
14
HDL symbol generator
hdl vhdl symbol verilog
Created 2017-01-26
38 commits to master branch, last one 7 years ago
stnolting
neoTRNG stnolting
21
175
bsd-3-clause
6
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
hdl rng rtl asic fpga trng vhdl chaos random entropy neorv32 asic-design cryptography key-generator entropy-source ring-oscillator random-number-generators
Created 2021-11-21
102 commits to main branch, last one about a month ago
aappleby
metron aappleby
14
164
mit
9
A C++ to Verilog translation tool with some basic guarantees that your code will work.
c cpp hdl fpga verilog compiler transpiler
Created 2019-11-25
1,758 commits to master branch, last one about a month ago
im-tomu
fomu-workshop im-tomu
64
162
apache-2.0
13
Support files for participating in a Fomu workshop
hdl fomu fpga vhdl litex migen riscv chisel verilog fomu-workshop
Created 2019-08-16
661 commits to master branch, last one 9 months ago
furrtek
SiliconRE furrtek
12
157
gpl-2.0
18
Traces, schematics, and general infos about custom chips reverse-engineered from silicon
hdl asic chip cpld fpga decap repro taito arcade konami silicon verilog gate-array video-game arcade-game standard-cell reverse-engineering
Created 2019-12-27
173 commits to master branch, last one 21 days ago