22 results found Sort:

VUnit
vunit VUnit
249
692
other
52
VUnit is a unit testing framework for VHDL/SystemVerilog
asic fpga vhdl testbench verilog-hdl unit-testing verification systemverilog-hdl universal-verification-methodology
Created 2014-11-18
2,045 commits to master branch, last one a day ago
ultraembedded
cores ultraembedded
199
645
unknown
47
Various HDL (Verilog) IP Cores
i2s rtl spi usb asic fpga sram uart audio sdram verilog verilator verilog-hdl verilog-components
Created 2015-05-30
54 commits to master branch, last one 2 years ago
PyHDI
Pyverilog PyHDI
166
576
apache-2.0
41
Python-based Hardware Design Processing Toolkit for Verilog HDL
parser python compiler hardware verilog-hdl code-generator dataflow-analyzer control-flow-analyzer
Created 2013-12-02
364 commits to develop branch, last one about a year ago
sudhamshu091
32-Verilog-Mini-Projects sudhamshu091
95
484
other
8
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and...
verilog miniproject verilog-hdl verilog-project
Created 2020-12-02
315 commits to main branch, last one about a year ago
NNgen
nngen NNgen
45
323
apache-2.0
20
NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
onnx python compiler hardware pyverilog veriloggen verilog-hdl deep-learning neural-network high-level-synthesis
Created 2019-11-12
448 commits to develop branch, last one 7 months ago
PyHDI
veriloggen PyHDI
57
298
apache-2.0
34
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
python compiler hardware pyverilog verilog-hdl high-level-synthesis hardware-construction-language
Created 2015-06-21
1,990 commits to develop branch, last one 9 months ago
mshr-h
vscode-verilog-hdl-support mshr-h
75
282
mit
9
HDL support for VS Code
svls ctags vivado vscode verilog iverilog modelsim verilator verilog-hdl hacktoberfest systemverilog icarus-verilog systemverilog-support bluespec-systemverilog language-server-client
Created 2015-12-10
535 commits to main branch, last one about a month ago
dpretet
async_fifo dpretet
68
213
other
10
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
cdc hdl asic fifo fpga async verilog synthesis verilator fifo-cache fifo-queue asic-design verilog-hdl verification icarus-verilog cross-clock-domain
Created 2017-03-28
49 commits to master branch, last one about a month ago
ultraembedded
core_jpeg ultraembedded
38
191
apache-2.0
10
High throughput JPEG decoder in Verilog for FPGA
fpga mjpeg verilog axi-stream motion-jpeg verilog-hdl jpeg-decoder
Created 2020-10-18
12 commits to main branch, last one 3 years ago
Gowtham1729
Image-Processing Gowtham1729
36
164
apache-2.0
4
Image Processing Toolbox in Verilog using Basys3 FPGA
coe ram fpga vhdl basys hsync pixel basys3 python vivado python3 verilog basys-board basys3-fpga convolution motion-blur verilog-hdl digital-systems verilog-project image-processing
Created 2018-12-04
44 commits to master branch, last one 8 months ago
AUCOHL
Fault AUCOHL
24
116
apache-2.0
8
A complete open-source design-for-testing (DFT) Solution
dft eda atpg jtag testing verilog stuck-at vlsi-cad scan-chains verilog-hdl fault-simulation
Created 2019-06-08
203 commits to main branch, last one 4 months ago
thedatabusdotio
fpga-ml-accelerator thedatabusdotio
23
97
unknown
3
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
asic fpga vhdl hardware verilog-hdl verification digital-design
Created 2020-07-17
6 commits to master branch, last one 11 days ago
ben-marshall
uart ben-marshall
19
84
mit
4
A simple implementation of a UART modem in Verilog.
fpga uart verilog hardware verilog-hdl uart-verilog
Created 2017-02-04
50 commits to master branch, last one 2 years ago
Jed-Z
computer-organization-lab Jed-Z
27
74
unknown
3
中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU
cpu sysu mips-cpu cpu-designs verilog-hdl
Created 2019-01-26
10 commits to master branch, last one 3 years ago
bojackchen
digital-flow bojackchen
26
71
unknown
4
This is a tutorial on standard digital design flow
synopsys synthesis verilog-hdl logic-synthesis timing-analysis
Created 2018-05-12
45 commits to master branch, last one 3 years ago
snbk001
Verilog-Design-Examples snbk001
12
64
unknown
1
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion,...
verilog testbenches verilog-hdl verilog-code self-checking verilog-design verilog-project verilog-programs
Created 2022-01-14
102 commits to main branch, last one about a year ago
michaelehab
AES-Verilog michaelehab
14
55
unknown
2
Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
aes rtl fpga learn aes-128 aes-192 aes-256 verilog fpga-soc security encryption fpga-board verilog-hdl cryptography aes-decryption aes-encryption verilog-project encryption-decryption
Created 2022-04-30
45 commits to main branch, last one about a year ago
RuSys
Verugent RuSys
4
53
apache-2.0
6
Verilog generation tool written in Rust
rust verilog-hdl verilog-verugent
Created 2018-07-26
51 commits to master branch, last one 11 months ago
TheSUPERCD
8bit_MicroComputer_Verilog TheSUPERCD
13
44
mit
2
This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and mod...
8bit verilog iverilog ben-eater verilog-hdl verilog-code ben-eaters-cpu verilog-project
Created 2020-01-14
27 commits to master branch, last one about a year ago
metr0jw
Spiking-Neural-Network-on-FPGA metr0jw
4
37
mit
2
Leaky Integrate and Fire (LIF) model implementation for FPGA
snn verilog lif-model lif-neuron verilog-hdl neuromorphic-computing spiking-neural-network spiking-neural-networks computational-neuroscience leaky-integrate-and-fire-model leaky-integrate-and-fire-neuron
Created 2023-01-17
18 commits to main branch, last one 7 months ago
ekb0412
100DaysofRTL ekb0412
7
30
apache-2.0
2
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
asic fpga verilog-hdl vlsi-design xilinx-vivado digital-system-design
Created 2023-03-26
180 commits to main branch, last one 10 months ago
Eyantra698Sumanto
Spice-to-Verilog-Converter Eyantra698Sumanto
2
11
gpl-3.0
1
Spice to Verilog Converter
spice analog verilog verilog-hdl system-verilog
Created 2022-06-03
11 commits to main branch, last one about a year ago