3 results found Sort:

ultraembedded
core_jpeg ultraembedded
42
220
apache-2.0
10
High throughput JPEG decoder in Verilog for FPGA
fpga mjpeg verilog axi-stream motion-jpeg verilog-hdl jpeg-decoder
Created 2020-10-18
12 commits to main branch, last one 4 years ago
KastnerRG
cgra4ml KastnerRG
10
70
apache-2.0
1
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
ai cnn dnn asic fpga hls4ml verilog axi-stream asic-design systemverilog neural-network
Created 2020-07-12
1,138 commits to master branch, last one 2 months ago
alknvl
axis_udp alknvl
22
46
mit
2
This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G ...
udp fpga verilog axi-stream
Created 2022-03-15
3 commits to main branch, last one 2 years ago