alknvl / axis_udp

This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core

alknvl
alknvl
Date Created 2022-03-15 (3 years ago)
Commits 3 (last one 3 years ago)
Stargazers 48 (0 this week)
Watchers 2 (0 this week)
Forks 23
License mit
Ranking

RepositoryStats indexes 628,868 repositories, of these alknvl/axis_udp is ranked #500,641 (20th percentile) for total stargazers, and #479,711 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #456/613.

alknvl/axis_udp is also tagged with popular topics, for these it's ranked: fpga (#437/510),  verilog (#261/306)

All Topics
udp fpga verilog axi-stream

Star History

Github stargazers over time

505045454040353530302525202015151010550020232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Watcher History

Github watchers over time, collection started in '23

33332222221111Jul '24Jul '24Aug '24Aug '24Sep '24Sep '24Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25

Recent Commit History

3 commits on the default branch (main) since jan '22

332.52.5221.51.5110.50.500Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Yearly Commits

Commits to the default branch (main) per year

332.52.5221.51.5110.50.5002022202220242024

Issue History

No issues have been posted

Languages

The primary language is Verilog but there's also others...

VerilogVerilogSystemVerilogSystemVerilogPythonPython

updated: 2025-02-23 @ 07:59am, id: 470158975 / R_kgDOHAYOfw