alknvl / axis_udp

This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core

Date Created 2022-03-15 (2 years ago)

Commits 3 (last one 2 years ago)

Stargazers 44 (0 this week)

Watchers 2 (0 this week)

Forks 22

License mit

Ranking

RepositoryStats indexes 584,777 repositories, of these alknvl/axis_udp is ranked #493,579 (16th percentile) for total stargazers, and #478,954 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #438/535.

alknvl/axis_udp is also tagged with popular topics, for these it's ranked: fpga (#424/478), verilog (#250/282)

All Topics

udp fpga verilog axi-stream

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Recent Commit History

3 commits on the default branch (main) since jan '22

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No issues have been posted

Languages

The primary language is Verilog but there's also others...

updated: 2024-11-20 @ 01:42pm, id: 470158975 / R_kgDOHAYOfw