Statistics for language Verilog
RepositoryStats tracks 630,040 Github repositories, of these 615 are reported to use a primary language of Verilog.
Most starred repositories for language Verilog (view more)
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A Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.
FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
A Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.
A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。
A Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
A Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.
FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com
A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
A Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.
efficient anti side channel SHA3 algorithm software and hardware co-design
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
A Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.
If you are interested in Digital Hardware Design and/or interested in chip and VLSI design, you may like this repo!
efficient anti side channel SHA3 algorithm software and hardware co-design
Affordable 2 GHz 3.2 GS/s 12 bit open-source open-hardware expandable USB oscilloscope
Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
A Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.
The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com
Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit
pcileech-fpga with wireless card emulation (D-Link DWA-556 Xtreme N PCIe Desktop Adapter)
efficient anti side channel SHA3 algorithm software and hardware co-design
