Statistics for language Verilog

RepositoryStats tracks 579,582 Github repositories, of these 533 are reported to use a primary language of Verilog.

Most starred repositories for language Verilog (view more)

755
3.1k
isc
168
PicoRV32 - A Size-Optimized RISC-V CPU
Created 2015-06-06
610 commits to main branch, last one 4 months ago
Verilog Ethernet components for FPGA implementation
Created 2014-11-19
1,202 commits to master branch, last one 8 months ago
285
2.1k
bsd-3-clause
94
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Created 2018-08-19
341 commits to master branch, last one 27 days ago
IC design and development should be faster,simpler and more reliable
Created 2019-10-19
41 commits to master branch, last one 2 years ago
568
1.7k
other
167
RTL, Cmodel, and testbench for NVDLA
Created 2017-09-26
102 commits to nvdlav1 branch, last one 6 years ago
416
1.7k
other
88
Open source FPGA-based NIC and platform for in-network compute
Created 2019-07-15
3,255 commits to master branch, last one 11 months ago

Trending repositories for language Verilog (view more)