Statistics for language Verilog

RepositoryStats tracks 598,730 Github repositories, of these 567 are reported to use a primary language of Verilog.

Most starred repositories for language Verilog (view more)

picorv32 YosysHQ

766

3.2k

isc

167

PicoRV32 - A Size-Optimized RISC-V CPU

Created 2015-06-06

610 commits to main branch, last one 6 months ago

verilog-ethernet alexforencich

710

2.4k

mit

119

Verilog Ethernet components for FPGA implementation

Created 2014-11-19

1,202 commits to master branch, last one 10 months ago

darkriscv darklife

290

2.2k

bsd-3-clause

94

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

cpu rtl core fpga riscv rv32e rv32i risc-v verilog softcore processor processor-design

Created 2018-08-19

344 commits to master branch, last one 3 days ago

wujian100_open XUANTIE-RV

573

1.9k

mit

140

IC design and development should be faster，simpler and more reliable

Created 2019-10-19

41 commits to master branch, last one 3 years ago

572

1.8k

other

167

RTL, Cmodel, and testbench for NVDLA

Created 2017-09-26

102 commits to nvdlav1 branch, last one 6 years ago

corundum corundum

427

1.8k

other

88

Open source FPGA-based NIC and platform for in-network compute

nic fpga linux networking in-network-compute

Created 2019-07-15

3,255 commits to master branch, last one about a year ago

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