Statistics for language Verilog

Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit

PicoRV32 - A Size-Optimized RISC-V CPU

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

Verilog Ethernet components for FPGA implementation

CPU Design Based on RISCV ISA

Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit

CPU Design Based on RISCV ISA

This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G ...

Amiga Minimig ported to the Tang Nano 20k FPGA

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

An open source GPU based off of the AMD Southern Islands ISA.

PicoRV32 - A Size-Optimized RISC-V CPU

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit

CPU Design Based on RISCV ISA

Opensource DDR3 Controller

This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G ...

Amiga Minimig ported to the Tang Nano 20k FPGA

CPU Design Based on RISCV ISA

Verilog AXI components for FPGA implementation

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit

CPU Design Based on RISCV ISA

PicoRV32 - A Size-Optimized RISC-V CPU

Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit

Opensource DDR3 Controller

building blocks for accelerating ZK proofs over binary fields

Amiga Minimig ported to the Tang Nano 20k FPGA

Turbo9 - Pipelined 6809 Microprocessor IP

Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

No description

pcileech-fpga with wireless card emulation

Turbo9 - Pipelined 6809 Microprocessor IP

A compact USB HID host FPGA core supporting keyboards, mice and gamepads.

Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog Ethernet components for FPGA implementation

PicoRV32 - A Size-Optimized RISC-V CPU

Verilog AXI components for FPGA implementation

All in one vscode plugin for HDL development

pcileech-fpga with wireless card emulation

Mega Drive/Genesis core written in Verilog

You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size of the systolic array can be changed, now it is 16X16.

Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)