Statistics for language Verilog

RepositoryStats tracks 641,239 Github repositories, of these 633 are reported to use a primary language of Verilog.

Most starred repositories for language Verilog (view more)

815
3.4k
isc
172
PicoRV32 - A Size-Optimized RISC-V CPU
Created 2015-06-06
610 commits to main branch, last one 10 months ago
Verilog Ethernet components for FPGA implementation
Created 2014-11-19
1,203 commits to master branch, last one about a month ago
300
2.3k
bsd-3-clause
93
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Created 2018-08-19
417 commits to master branch, last one 7 days ago
IC design and development should be faster,simpler and more reliable
Created 2019-10-19
41 commits to master branch, last one 3 years ago
634
1.9k
bsd-3-clause
51
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Created 2019-10-28
29,015 commits to master branch, last one 8 hours ago
442
1.9k
other
87
Open source FPGA-based NIC and platform for in-network compute
Created 2019-07-15
3,255 commits to master branch, last one about a year ago

Trending repositories for language Verilog (view more)