Statistics for language Verilog
RepositoryStats tracks 609,393 Github repositories, of these 592 are reported to use a primary language of Verilog.
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Traces, schematics, and general infos about custom chips reverse-engineered from silicon
FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
Traces, schematics, and general infos about custom chips reverse-engineered from silicon
My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
Affordable 2 GHz 3.2 GS/s 12 bit open-source open-hardware expandable USB oscilloscope
FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
This repository houses the ModRetro Chromatic's FPGA design files.
Affordable 2 GHz 3.2 GS/s 12 bit open-source open-hardware expandable USB oscilloscope
TJ-数字逻辑大作业。基于Vivado平台、Verilog语言编写、VGA，mp3，键盘作为外设的接木块游戏。同济大学数字逻辑大作业
Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
pcileech-fpga with wireless card emulation (D-Link DWA-556 Xtreme N PCIe Desktop Adapter)
Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
