Statistics for topic riscv
RepositoryStats tracks 584,797 Github repositories, of these 166 are tagged with the riscv topic. The most common primary language for repositories using this topic is C (32). Other languages include: Rust (27), C++ (16), Verilog (16), SystemVerilog (12)
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ncnn is a high-performance neural network inference framework optimized for the mobile platform
A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.
Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards
A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriC...
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
A header only library implementing common mathematical functions using SIMD intrinsics
A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host
A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.
ncnn is a high-performance neural network inference framework optimized for the mobile platform
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host
Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards
An unofficial reference implementation of the C Minus Minus Compiler
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
A header only library implementing common mathematical functions using SIMD intrinsics
A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.
ncnn is a high-performance neural network inference framework optimized for the mobile platform
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriC...
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
Assured confidential execution (ACE) implements VM-based trusted execution environment (TEE) for RISC-V with focus on a formally verified and auditable security monitor.
a game where you're given a potato and your job is to implement a firmware for it
Apache NuttX RTOS on 64-bit RISC-V Sophgo SG2000 (T-Head C906 / Milk-V Duo S)
A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
ncnn is a high-performance neural network inference framework optimized for the mobile platform
A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriC...
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
A fully compliant RISC-V computer made inside the game Terraria
a game where you're given a potato and your job is to implement a firmware for it
Методические материалы по разработке процессора архитектуры RISC-V
RISC-V Embedded Processor for Approximate Computing
A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave