Statistics for topic riscv
RepositoryStats tracks 579,129 Github repositories, of these 165 are tagged with the riscv topic. The most common primary language for repositories using this topic is C (32). Other languages include: Rust (27), C++ (16), Verilog (16), SystemVerilog (12)
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ncnn is a high-performance neural network inference framework optimized for the mobile platform
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
This project aims to build an Embedded Linux System, in order to analyze the chip from the power-on execution of the first instruction to the entire system running, based on qemu simulator development...
Методические материалы по разработке процессора архитектуры RISC-V
ncnn is a high-performance neural network inference framework optimized for the mobile platform
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
This project aims to build an Embedded Linux System, in order to analyze the chip from the power-on execution of the first instruction to the entire system running, based on qemu simulator development...
Методические материалы по разработке процессора архитектуры RISC-V
ncnn is a high-performance neural network inference framework optimized for the mobile platform
A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriC...
Symbolic execution for RISC-V machine code based on the formal LibRISCV ISA model
a game where you're given a potato and your job is to implement a firmware for it
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
a game where you're given a potato and your job is to implement a firmware for it
Apache NuttX RTOS on 64-bit RISC-V Sophgo SG2000 (T-Head C906 / Milk-V Duo S)
A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
ncnn is a high-performance neural network inference framework optimized for the mobile platform
A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriC...
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
A fully compliant RISC-V computer made inside the game Terraria
a game where you're given a potato and your job is to implement a firmware for it
Методические материалы по разработке процессора архитектуры RISC-V
RISC-V Embedded Processor for Approximate Computing
A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave