Statistics for topic riscv
RepositoryStats tracks 640,565 Github repositories, of these 181 are tagged with the riscv topic. The most common primary language for repositories using this topic is C (34). Other languages include: Rust (28), C++ (18), Verilog (16), SystemVerilog (14), Scala (12)
Stargazers over time for topic riscv
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ncnn is a high-performance neural network inference framework optimized for the mobile platform
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards
A curated list of awesome MangoPi MQ-Pro images, tools and resources
Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards
Maix Speech AI lib, a fast and small speech lib running on embedded devices, including ASR, chat, TTS etc.
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
ncnn is a high-performance neural network inference framework optimized for the mobile platform
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriC...
A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM, 8-bit AVR and 32-bit RISC-V architectures.
Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards
A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
Learn how to build our own RV32I core and use it on FPGA.
Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
ncnn is a high-performance neural network inference framework optimized for the mobile platform
A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM, 8-bit AVR and 32-bit RISC-V architectures.
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
Modern, advanced, portable, multiprotocol bootloader and boot manager.
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriC...
Machine-readable database of the RISC-V specification, and tools to generate various views
Learn how to build our own RV32I core and use it on FPGA.
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
a game where you're given a potato and your job is to implement a firmware for it
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
Machine-readable database of the RISC-V specification, and tools to generate various views
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...
ncnn is a high-performance neural network inference framework optimized for the mobile platform
A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM, 8-bit AVR and 32-bit RISC-V architectures.
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriC...
a game where you're given a potato and your job is to implement a firmware for it
Learn how to build our own RV32I core and use it on FPGA.
A translator from ARM NEON intrinsics to RISCV-V Extension implementation