Statistics for topic riscv
RepositoryStats tracks 595,857 Github repositories, of these 167 are tagged with the riscv topic. The most common primary language for repositories using this topic is C (31). Other languages include: Rust (27), C++ (16), Verilog (16), SystemVerilog (13)
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ncnn is a high-performance neural network inference framework optimized for the mobile platform
A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriC...
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards
a game where you're given a potato and your job is to implement a firmware for it
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC,包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
ncnn is a high-performance neural network inference framework optimized for the mobile platform
A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriC...
Modern, advanced, portable, multiprotocol bootloader and boot manager.
An unofficial reference implementation of the C Minus Minus Compiler
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.
ncnn is a high-performance neural network inference framework optimized for the mobile platform
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriC...
a game where you're given a potato and your job is to implement a firmware for it
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
a game where you're given a potato and your job is to implement a firmware for it
Assured confidential execution (ACE) implements VM-based trusted execution environment (TEE) for RISC-V with focus on a formally verified and auditable security monitor.
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
a game where you're given a potato and your job is to implement a firmware for it
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
Apache NuttX RTOS on 64-bit RISC-V Sophgo SG2000 (T-Head C906 / Milk-V Duo S)
A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
ncnn is a high-performance neural network inference framework optimized for the mobile platform
A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriC...
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
a game where you're given a potato and your job is to implement a firmware for it
A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
RISC-V Embedded Processor for Approximate Computing
Методические материалы по разработке процессора архитектуры RISC-V