Trending repositories for topic riscv

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

ncnn is a high-performance neural network inference framework optimized for the mobile platform

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

This project aims to build an Embedded Linux System, in order to analyze the chip from the power-on execution of the first instruction to the entire system running, based on qemu simulator development...

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

A FPGA friendly 32 bit RISC-V CPU implementation

An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriC...

The Ultra-Low Power RISC-V Core

Peripheral Access Crates for Espressif SoCs and modules

RISC-V Debug Support for our PULP RISC-V Cores

Reference implementation for the book "Writing a RISC-V Emulator in Rust".

An unofficial assembly reference for RISC-V.

3-stage RV32IMACZb* processor with debug

RARS -- RISC-V Assembler and Runtime Simulator

Unix-like OS in Rust inspired by xv6-riscv

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

This project aims to build an Embedded Linux System, in order to analyze the chip from the power-on execution of the first instruction to the entire system running, based on qemu simulator development...

Peripheral Access Crates for Espressif SoCs and modules

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

RISC-V Debug Support for our PULP RISC-V Cores

An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.

Reference implementation for the book "Writing a RISC-V Emulator in Rust".

An unofficial assembly reference for RISC-V.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

The Ultra-Low Power RISC-V Core

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

3-stage RV32IMACZb* processor with debug

A FPGA friendly 32 bit RISC-V CPU implementation

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

RARS -- RISC-V Assembler and Runtime Simulator

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

Unix-like OS in Rust inspired by xv6-riscv

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

ncnn is a high-performance neural network inference framework optimized for the mobile platform

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

ncnn is a high-performance neural network inference framework optimized for the mobile platform

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

The fastest RISC-V sandbox

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

This project aims to build an Embedded Linux System, in order to analyze the chip from the power-on execution of the first instruction to the entire system running, based on qemu simulator development...

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

3-stage RV32IMACZb* processor with debug

An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

The Ultra-Low Power RISC-V Core

Compact and Efficient RISC-V RV32I[MAFC] emulator

RARS -- RISC-V Assembler and Runtime Simulator

Modern, advanced, portable, multiprotocol bootloader and boot manager.

A FPGA friendly 32 bit RISC-V CPU implementation

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriC...

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...

a game where you're given a potato and your job is to implement a firmware for it

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...

A translator from ARM NEON intrinsics to RISCV-V Extension implementation

This project aims to build an Embedded Linux System, in order to analyze the chip from the power-on execution of the first instruction to the entire system running, based on qemu simulator development...

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

The fastest RISC-V sandbox

Compact and Efficient RISC-V RV32I[MAFC] emulator

a game where you're given a potato and your job is to implement a firmware for it

3-stage RV32IMACZb* processor with debug

An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.

Peripheral Access Crates for Espressif SoCs and modules

Arduino compatible Risc-V Based SOC

No PR will be accepted for now, but feel free to submit issue, very appreciated.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

A Toolchain to make Build and Run eBPF programs easier

RISC-V Debug Support for our PULP RISC-V Cores

RARS -- RISC-V Assembler and Runtime Simulator

VeeR EL2 Core

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...

ncnn is a high-performance neural network inference framework optimized for the mobile platform

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriC...

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

A fully compliant RISC-V computer made inside the game Terraria

The Ultra-Low Power RISC-V Core

The fastest RISC-V sandbox

Modern, advanced, portable, multiprotocol bootloader and boot manager.

3-stage RV32IMACZb* processor with debug

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Rocket Chip Generator

The RISC-V Virtual Machine

An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

SonicBOOM: The Berkeley Out-of-Order Machine

RISC-V Linux SoC, marchID: 0x2b

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

A translator from ARM NEON intrinsics to RISCV-V Extension implementation

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

The fastest RISC-V sandbox

Open-Source Posit RISC-V Core with Quire Capability

An unofficial reference implementation of the C Minus Minus Compiler

This project aims to build an Embedded Linux System, in order to analyze the chip from the power-on execution of the first instruction to the entire system running, based on qemu simulator development...

Assured confidential execution (ACE) implements VM-based trusted execution environment (TEE) for RISC-V with focus on a formally verified and auditable security monitor.

a game where you're given a potato and your job is to implement a firmware for it

Unit tests generator for RVV 1.0

RISC-V Debug Support for our PULP RISC-V Cores

📦 Prebuilt RISC-V GCC toolchains for x64 Linux.

Very small, safe, lightning fast, yet portable preemptive RTOS with SMP support

A curated list of awesome MangoPi MQ-Pro images, tools and resources

3-stage RV32IMACZb* processor with debug

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave

The Ultra-Low Power RISC-V Core

No PR will be accepted for now, but feel free to submit issue, very appreciated.

a game where you're given a potato and your job is to implement a firmware for it

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

RiscV based SOC with 2D and 3D graphics acceleration for Tang Nano 20K

Apache NuttX RTOS on 64-bit RISC-V Sophgo SG2000 (T-Head C906 / Milk-V Duo S)

A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...

ncnn is a high-performance neural network inference framework optimized for the mobile platform

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriC...

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

3-stage RV32IMACZb* processor with debug

A fully compliant RISC-V computer made inside the game Terraria

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

Unix-like OS in Rust inspired by xv6-riscv

Modern, advanced, portable, multiprotocol bootloader and boot manager.

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

A self-hosting and educational C optimizing compiler

A FPGA friendly 32 bit RISC-V CPU implementation

Rocket Chip Generator

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

The Ultra-Low Power RISC-V Core

The fastest RISC-V sandbox

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

RISC-V Linux SoC, marchID: 0x2b

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Rust version of THU uCore OS. Linux compatible.

a game where you're given a potato and your job is to implement a firmware for it

3-stage RV32IMACZb* processor with debug

A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave

RISC-V Embedded Processor for Approximate Computing

Методические материалы по разработке процессора архитектуры RISC-V

Unit tests generator for RVV 1.0

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Fast RISC-V-based scripting backend for game engines

Assured confidential execution (ACE) implements VM-based trusted execution environment (TEE) for RISC-V with focus on a formally verified and auditable security monitor.

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

An AXI4 crossbar implementation in SystemVerilog

A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw

A Single Cycle Risc-V 32 bit CPU

The fastest RISC-V sandbox

Very small, safe, lightning fast, yet portable preemptive RTOS with SMP support

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...

RISC-V out-of-order core for education and research purposes

RISC-V Linux SoC, marchID: 0x2b

A self-hosting and educational C optimizing compiler