Trending repositories for topic riscv

ncnn is a high-performance neural network inference framework optimized for the mobile platform

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriC...

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

Modern, advanced, portable, multiprotocol bootloader and boot manager.

The fastest RISC-V sandbox

RISC-V Linux SoC, marchID: 0x2b

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Rocket Chip Generator

A self-hosting and educational C optimizing compiler

RARS -- RISC-V Assembler and Runtime Simulator

SonicBOOM: The Berkeley Out-of-Order Machine

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A FPGA friendly 32 bit RISC-V CPU implementation

A header only library implementing common mathematical functions using SIMD intrinsics

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

A header only library implementing common mathematical functions using SIMD intrinsics

The fastest RISC-V sandbox

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

RISC-V Linux SoC, marchID: 0x2b

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Modern, advanced, portable, multiprotocol bootloader and boot manager.

A self-hosting and educational C optimizing compiler

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

RARS -- RISC-V Assembler and Runtime Simulator

SonicBOOM: The Berkeley Out-of-Order Machine

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Rocket Chip Generator

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriC...

A FPGA friendly 32 bit RISC-V CPU implementation

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

ncnn is a high-performance neural network inference framework optimized for the mobile platform

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriC...

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Modern, advanced, portable, multiprotocol bootloader and boot manager.

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

The Ultra-Low Power RISC-V Core

Rocket Chip Generator

Rust version of THU uCore OS. Linux compatible.

RISC-V Linux SoC, marchID: 0x2b

SonicBOOM: The Berkeley Out-of-Order Machine

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A FPGA friendly 32 bit RISC-V CPU implementation

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

The fastest RISC-V sandbox

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

A fully compliant RISC-V computer made inside the game Terraria

Unit tests generator for RVV 1.0

An unofficial reference implementation of the C Minus Minus Compiler

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

Peripheral Access Crates for Espressif SoCs and modules

A header only library implementing common mathematical functions using SIMD intrinsics

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Sedna - a pure Java RISC-V emulator.

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

RISC-V Linux SoC, marchID: 0x2b

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Методические материалы по разработке процессора архитектуры RISC-V

The fastest RISC-V sandbox

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

World Of Warcraft 3.3.5a server

The Ultra-Low Power RISC-V Core

Compact and Efficient RISC-V RV32I[MAFC] emulator

An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

ncnn is a high-performance neural network inference framework optimized for the mobile platform

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriC...

Rocket Chip Generator

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

A FPGA friendly 32 bit RISC-V CPU implementation

SonicBOOM: The Berkeley Out-of-Order Machine

Modern, advanced, portable, multiprotocol bootloader and boot manager.

The Ultra-Low Power RISC-V Core

A fully compliant RISC-V computer made inside the game Terraria

The RISC-V Virtual Machine

3-stage RV32IMACZb* processor with debug

oreboot is a fork of coreboot, with C removed, written in Rust.

Rust version of THU uCore OS. Linux compatible.

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see https://github.com/rustsbi/prototyper.

A Single Cycle Risc-V 32 bit CPU

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

第十六届智能车竞赛-国家级一等奖-嵌入式控制开源(恩智浦杯/飞思卡尔杯)-全国第14名 🏆

Assured confidential execution (ACE) implements VM-based trusted execution environment (TEE) for RISC-V with focus on a formally verified and auditable security monitor.

Peripheral Access Crates for Espressif SoCs and modules

IEEE 754 single and double precision floating point library in systemverilog and vhdl

Unit tests generator for RVV 1.0

Build embedded applications with the IAR Build Tools on Docker Containers

No PR will be accepted for now, but feel free to submit issue, very appreciated.

Very small, safe, lightning fast, yet portable preemptive RTOS with SMP support

a game where you're given a potato and your job is to implement a firmware for it

3-stage RV32IMACZb* processor with debug

UNIX-like operating system written in C and C++

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

This project aims to build an Embedded Linux System, in order to analyze the chip from the power-on execution of the first instruction to the entire system running, based on qemu simulator development...

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

Методические материалы по разработке процессора архитектуры RISC-V

An AXI4 crossbar implementation in SystemVerilog

A header only library implementing common mathematical functions using SIMD intrinsics

Simple risc-v emulator, able to run linux, written in C.

a game where you're given a potato and your job is to implement a firmware for it

RiscV based SOC with 2D and 3D graphics acceleration for Tang Nano 20K

Apache NuttX RTOS on 64-bit RISC-V Sophgo SG2000 (T-Head C906 / Milk-V Duo S)

A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave

ncnn is a high-performance neural network inference framework optimized for the mobile platform

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriC...

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

A fully compliant RISC-V computer made inside the game Terraria

3-stage RV32IMACZb* processor with debug

Unix-like OS in Rust inspired by xv6-riscv

Modern, advanced, portable, multiprotocol bootloader and boot manager.

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

A self-hosting and educational C optimizing compiler

A FPGA friendly 32 bit RISC-V CPU implementation

Rocket Chip Generator

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

The Ultra-Low Power RISC-V Core

RISC-V Linux SoC, marchID: 0x2b

The fastest RISC-V sandbox

Rust version of THU uCore OS. Linux compatible.

a game where you're given a potato and your job is to implement a firmware for it

3-stage RV32IMACZb* processor with debug

Методические материалы по разработке процессора архитектуры RISC-V

RISC-V Embedded Processor for Approximate Computing

A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave

Fast RISC-V-based scripting backend for game engines

Unit tests generator for RVV 1.0

A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

RISC-V out-of-order core for education and research purposes

A Single Cycle Risc-V 32 bit CPU

A unified software platform for embedded system projects ...

Apache NuttX RTOS for Pine64 Ox64 64-bit RISC-V SBC (BouffaloLab BL808)

An AXI4 crossbar implementation in SystemVerilog

Assured confidential execution (ACE) implements VM-based trusted execution environment (TEE) for RISC-V with focus on a formally verified and auditable security monitor.

Very small, safe, lightning fast, yet portable preemptive RTOS with SMP support

The fastest RISC-V sandbox

RISC-V Linux SoC, marchID: 0x2b