Trending repositories for topic riscv

ncnn is a high-performance neural network inference framework optimized for the mobile platform

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

C++20 RISC-V RV32/64/128 userspace emulator library

A fully compliant RISC-V computer made inside the game Terraria

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webass...

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

Build, Distribute and Run CO-RE eBPF programs easier with JSON and Webassembly OCI images

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

phoeniX RISC-V Processor

A FPGA friendly 32 bit RISC-V CPU implementation

Tengine is a lite, high performance, modular inference engine for embedded device

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

RISC-V Linux SoC, marchID: 0x2b

An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.

RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

The RISC-V Virtual Machine

The Ultra-Low Power RISC-V Core

Unix-like OS in Rust inspired by xv6-riscv

:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

phoeniX RISC-V Processor

C++20 RISC-V RV32/64/128 userspace emulator library

Build, Distribute and Run CO-RE eBPF programs easier with JSON and Webassembly OCI images

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

RISC-V Linux SoC, marchID: 0x2b

An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.

A fully compliant RISC-V computer made inside the game Terraria

RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

The RISC-V Virtual Machine

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

The Ultra-Low Power RISC-V Core

A FPGA friendly 32 bit RISC-V CPU implementation

ncnn is a high-performance neural network inference framework optimized for the mobile platform

Unix-like OS in Rust inspired by xv6-riscv

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webass...

:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

SonicBOOM: The Berkeley Out-of-Order Machine

ncnn is a high-performance neural network inference framework optimized for the mobile platform

phoeniX RISC-V Processor

C++20 RISC-V RV32/64/128 userspace emulator library

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

A fully compliant RISC-V computer made inside the game Terraria

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webass...

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Build, Distribute and Run CO-RE eBPF programs easier with JSON and Webassembly OCI images

An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.

Rocket Chip Generator

RISC-V Linux SoC, marchID: 0x2b

SonicBOOM: The Berkeley Out-of-Order Machine

A FPGA friendly 32 bit RISC-V CPU implementation

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Unix-like OS in Rust inspired by xv6-riscv

:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Fast RISC-V-based scripting backend for game engines

phoeniX RISC-V Processor

C++20 RISC-V RV32/64/128 userspace emulator library

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

Fast RISC-V-based scripting backend for game engines

Build, Distribute and Run CO-RE eBPF programs easier with JSON and Webassembly OCI images

An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.

RISC-V Linux SoC, marchID: 0x2b

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

A fully compliant RISC-V computer made inside the game Terraria

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Unix-like OS in Rust inspired by xv6-riscv

SonicBOOM: The Berkeley Out-of-Order Machine

:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

The RISC-V Virtual Machine

ncnn is a high-performance neural network inference framework optimized for the mobile platform

A fully compliant RISC-V computer made inside the game Terraria

Unix-like OS in Rust inspired by xv6-riscv

C++20 RISC-V RV32/64/128 userspace emulator library

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webass...

phoeniX RISC-V Processor

A FPGA friendly 32 bit RISC-V CPU implementation

Rocket Chip Generator

SonicBOOM: The Berkeley Out-of-Order Machine

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

The Ultra-Low Power RISC-V Core

Build, Distribute and Run CO-RE eBPF programs easier with JSON and Webassembly OCI images

RARS -- RISC-V Assembler and Runtime Simulator

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.

RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see https://github.com/rustsbi/prototyper.

phoeniX RISC-V Processor

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

C++20 RISC-V RV32/64/128 userspace emulator library

An AXI4 crossbar implementation in SystemVerilog

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

Методические материалы по разработке процессора архитектуры RISC-V

Unix-like OS in Rust inspired by xv6-riscv

A minimalist RISC-V system emulator capable of running Linux kernel

Very small, safe, lightning fast, yet portable preemptive RTOS with SMP support

A model of the RISC Zero zkVM and ecosystem in the Lean 4 Theorem Prover

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

📦 Prebuilt RISC-V GCC toolchains for x64 Linux.

Fast RISC-V-based scripting backend for game engines

Build, Distribute and Run CO-RE eBPF programs easier with JSON and Webassembly OCI images

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

第十六届智能车竞赛-国家级一等奖-嵌入式控制开源(恩智浦杯/飞思卡尔杯)-全国第14名 🏆

An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.

RISC-V Debug Support for our PULP RISC-V Cores

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

RISC-V out-of-order core for education and research purposes

Методические материалы по разработке процессора архитектуры RISC-V

phoeniX RISC-V Processor

Apache NuttX RTOS for Pine64 Ox64 64-bit RISC-V SBC (BouffaloLab BL808)

JIT-accelerated RISC-V instruction set simulator

SharpRISCV is an implementation of RISC-V assembly in C#. First RISC V Assembly that build windows executable file

A fully compliant RISC-V computer made inside the game Terraria

ncnn is a high-performance neural network inference framework optimized for the mobile platform

Unix-like OS in Rust inspired by xv6-riscv

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webass...

A self-hosting and educational C optimizing compiler

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

Rocket Chip Generator

A FPGA friendly 32 bit RISC-V CPU implementation

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Rust version of THU uCore OS. Linux compatible.

The Ultra-Low Power RISC-V Core

:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Build, Distribute and Run CO-RE eBPF programs easier with JSON and Webassembly OCI images

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

RISC-V Linux SoC, marchID: 0x2b

SonicBOOM: The Berkeley Out-of-Order Machine

RARS -- RISC-V Assembler and Runtime Simulator

C++20 RISC-V RV32/64/128 userspace emulator library

A fully compliant RISC-V computer made inside the game Terraria

Unix-like OS in Rust inspired by xv6-riscv

phoeniX RISC-V Processor

Unit tests generator for RVV 1.0

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Fast RISC-V-based scripting backend for game engines

An operating system kernel for RISC-V and AArch64 SBCs

RISC-V out-of-order core for education and research purposes

A minimalist RISC-V system emulator capable of running Linux kernel

A unified software platform for embedded system projects ...

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

An AXI4 crossbar implementation in SystemVerilog

RISC-V Linux SoC, marchID: 0x2b

Very small, safe, lightning fast, yet portable preemptive RTOS with SMP support

No PR will be accepted for now, but feel free to submit issue, very appreciated.

Build, Distribute and Run CO-RE eBPF programs easier with JSON and Webassembly OCI images

This project aims to build an Embedded Linux System, in order to analyze the chip from the power-on execution of the first instruction to the entire system running, based on qemu simulator development...

A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw