pulp-platform / cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Date Created 2022-09-01 (2 years ago)

Commits 97 (last one about a month ago)

Stargazers 194 (0 this week)

Watchers 15 (0 this week)

Forks 46

License other

Ranking

RepositoryStats indexes 579,555 repositories, of these pulp-platform/cheshire is ranked #181,640 (69th percentile) for total stargazers, and #145,291 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #114/533.

pulp-platform/cheshire is also tagged with popular topics, for these it's ranked: simulation (#312/996), fpga (#152/475), riscv (#68/165)

Other Information

pulp-platform/cheshire has 22 open pull requests on Github, 94 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 7 open issues and 13 closed issues.

There have been 1 release, the latest one was published on 2024-10-02 (about a month ago) with the name v0.1.0.

All Topics

asic fpga riscv rtl-design simulation systemverilog

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

97 commits on the default branch (main) since jan '22

Yearly Commits

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-11-07 @ 07:24am, id: 531413954 / R_kgDOH6y7wg