pulp-platform / cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Date Created 2022-09-01 (2 years ago)

Commits 100 (last one 6 days ago)

Stargazers 199 (2 this week)

Watchers 15 (0 this week)

Forks 48

License other

Ranking

RepositoryStats indexes 584,353 repositories, of these pulp-platform/cheshire is ranked #179,469 (69th percentile) for total stargazers, and #145,605 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #113/535.

pulp-platform/cheshire is also tagged with popular topics, for these it's ranked: simulation (#310/1005), fpga (#152/478), riscv (#68/166)

Other Information

pulp-platform/cheshire has 19 open pull requests on Github, 97 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 7 open issues and 13 closed issues.

There have been 1 release, the latest one was published on 2024-10-02 (about a month ago) with the name v0.1.0.

All Topics

asic fpga riscv rtl-design simulation systemverilog

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

100 commits on the default branch (main) since jan '22

Yearly Commits

Commits to the default branch (main) per year

Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-11-21 @ 09:40am, id: 531413954 / R_kgDOH6y7wg