pulp-platform / cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Date Created 2022-09-01 (about a year ago)

Commits 86 (last one about a month ago)

Stargazers 134 (4 this week)

Watchers 13 (0 this week)

Forks 31

License other

Ranking

RepositoryStats indexes 523,840 repositories, of these pulp-platform/cheshire is ranked #219,880 (58th percentile) for total stargazers, and #160,252 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #53/152.

pulp-platform/cheshire is also tagged with popular topics, for these it's ranked: simulation (#381/902), fpga (#179/425), riscv (#72/146)

Other Information

pulp-platform/cheshire has 20 open pull requests on Github, 75 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 5 open issues and 7 closed issues.

All Topics

asic fpga riscv rtl-design simulation systemverilog

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

86 commits on the default branch (main) since jan '22

Yearly Commits

Commits to the default branch (main) per year

Issue History

Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-05-31 @ 06:11pm, id: 531413954 / R_kgDOH6y7wg