Search Results - RepositoryStats

skywater-pdk google

391

3.0k

apache-2.0

156

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

eda pdk asic magic openram openroad skywater asic-library

Created 2020-05-06

370 commits to main branch, last one about a year ago

cva6 openhwgroup

692

2.3k

other

92

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

cpu asic fpga ariane risc-v rv64gc systemverilog-hdl

Created 2018-01-23

7,234 commits to master branch, last one 18 hours ago

serv olofk

190

1.4k

isc

38

SERV - The SErial RISC-V CPU

asic fpga risc-v verilog

Created 2018-10-31

455 commits to main branch, last one 3 days ago

clash-compiler clash-lang

154

1.4k

other

55

Haskell to VHDL/Verilog/SystemVerilog compiler

asic fpga vhdl haskell verilog systemverilog hardware-description-language

Created 2013-07-04

6,050 commits to master branch, last one 21 days ago

OpenLane The-OpenROAD-Project

374

1.4k

apache-2.0

60

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

rtl asic vlsi 130nm magic yosys netgen caravel foundry klayout openram rtl2gds verilog openroad skywater soc-design system-on-chip

Created 2020-07-20

1,892 commits to master branch, last one about a month ago

riscv ultraembedded

235

1.3k

bsd-3-clause

51

RISC-V CPU Core (RV32IM)

cpu asic fpga rv32i risc-v rv32im verilog verilator riscv-linux verification pipeline-processor

Created 2014-08-31

48 commits to master branch, last one 3 years ago

axi pulp-platform

267

1.1k

other

39

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

ip axi rtl asic axi4 fpga hardware axi4-lite systemverilog network-on-chip

Created 2018-04-12

1,296 commits to master branch, last one 29 days ago

biriscv ultraembedded

147

868

apache-2.0

29

32-bit Superscalar RISC-V CPU

cpu asic fpga linux rv32i risc-v rv32im xilinx artix-7 verilog coremark in-order verilator riscv-linux superscalar branch-prediction pipelined-processors

Created 2020-02-10

37 commits to master branch, last one 3 years ago

dss esig

379

824

lgpl-2.1

116

Digital Signature Service : creation, extension and validation of advanced electronic signatures

asic java cades jades pades xades signature esignature validation

Created 2015-01-30

6,367 commits to master branch, last one 2 months ago

gemmini ucb-bar

170

818

other

30

Berkeley's Spatial Array Generator

dnn asic accelerator

Created 2018-10-31

738 commits to master branch, last one a day ago

vunit VUnit

263

742

other

51

VUnit is a unit testing framework for VHDL/SystemVerilog

asic fpga vhdl testbench verilog-hdl unit-testing verification systemverilog-hdl universal-verification-methodology

Created 2014-11-18

2,098 commits to master branch, last one 18 days ago

cores ultraembedded

215

710

unknown

48

Various HDL (Verilog) IP Cores

i2s rtl spi usb asic fpga sram uart audio sdram verilog verilator verilog-hdl verilog-components

Created 2015-05-30

54 commits to master branch, last one 3 years ago

Embedded-Neural-Network zssloth

120

555

unknown

92

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

asic fpga compression deep-learning neural-network

Created 2016-08-16

60 commits to master branch, last one 9 months ago

ara pulp-platform

132

379

other

23

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

ara cpu rvv asic riscv vector rv64gcv

Created 2021-03-05

1,700 commits to main branch, last one a day ago

gf180mcu-pdk google

53

372

apache-2.0

21

PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

eda pdk asic 180nm gf180mcu openroad globalfoundries

Created 2022-07-20

112 commits to main branch, last one about a year ago

tensil tensil-ai

29

360

other

10

Open source machine learning accelerators

hdl asic fpga scala silicon machine-learning artificial-intelligence

Created 2022-02-26

466 commits to main branch, last one 2 years ago

surf slaclab

57

347

other

49

A huge VHDL library for FPGA development

hdl asic fpga vhdl python firmware

Created 2016-08-23

7,639 commits to main branch, last one about a month ago

esp sld-columbia

107

343

other

25

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

asic fpga riscv accelerators system-on-chip network-on-chip embedded-systems

Created 2019-06-04

1,571 commits to main branch, last one 4 months ago

aes secworks

126

337

bsd-2-clause

27

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

aes asic fpga encryption block-cipher

Created 2014-02-21

684 commits to master branch, last one about a month ago

rggen rggen

43

334

mit

14

Code generation tool for control and status registers

apb axi csr eda ral rtl soc uvm amba asic fpga vhdl verilog wishbone-bus systemverilog uvm-ral-model wiki-documents uvm-register-model register-descriptions

Created 2019-04-10

379 commits to master branch, last one 8 days ago

mempool pulp-platform

45

274

apache-2.0

9

A 256-RISC-V-core system with low-latency access into shared L1 memory.

asic risc-v manycore

Created 2019-11-21

1,529 commits to main branch, last one about a month ago

awesome-dv troyguo

66

268

unknown

11

Awesome ASIC design verification

uvm asic verification asic-verification formal-verification

Created 2020-03-02

19 commits to master branch, last one 2 years ago

async_fifo dpretet

76

266

other

11

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

cdc hdl asic fifo fpga async verilog synthesis verilator fifo-cache fifo-queue asic-design verilog-hdl verification icarus-verilog cross-clock-domain

Created 2017-03-28

49 commits to master branch, last one 7 months ago

systemrdl-compiler SystemRDL

67

236

mit

27

SystemRDL 2.0 language compiler front-end

csr eda asic fpga registers systemrdl design-automation systemrdl-compiler register-descriptions hardware-description-language register-description-language

Created 2018-03-11

549 commits to main branch, last one 6 months ago

antminer-monitor anselal

146

228

gpl-3.0

35

Cryptocurrency ASIC mining hardware monitor using a simple web interface

asic dash avalon mining python bitcoin bitmain monitor antminer litecoin innosilicon hacktoberfest bitcoin-mining cryptocurrency mining-monitor antminer-monitor

Created 2017-09-25

212 commits to master branch, last one about a year ago

openlane2 efabless

38

211

apache-2.0

12

The next generation of OpenLane, rewritten from scratch with a modular architecture

drc eda lvs pdk pnr sta asic flow vlsi flows gdsii sky130 silicon verilog gf180mcu openlane openroad rtl-to-gds

Created 2023-01-16

399 commits to main branch, last one 12 days ago

livehd masc-ucsc

48

206

other

29

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

hdl asic fpga live lgraph synthesis simulation

Created 2018-04-23

6,528 commits to master branch, last one 2 months ago

GDS3D trilomix

34

201

gpl-2.0

8

GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called proce...

eda fem asic mesh gdsii 3d-models integrated-circuits

Created 2017-01-26

44 commits to master branch, last one 3 months ago

cheshire pulp-platform

48

200

other

15

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

asic fpga riscv rtl-design simulation systemverilog

Created 2022-09-01

100 commits to main branch, last one 8 days ago

open-register-design-tool Juniper

69

195

apache-2.0

44

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

eda uvm asic fpga jspec registers systemrdl systemverilog systemrdl-compiler register-descriptions

Created 2016-06-14

460 commits to master branch, last one about a month ago