Search Results - RepositoryStats

skywater-pdk google

406

3.1k

apache-2.0

158

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

eda pdk asic magic openram openroad skywater asic-library

Created 2020-05-06

370 commits to main branch, last one about a year ago

cva6 openhwgroup

747

2.4k

other

95

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

cpu asic fpga ariane risc-v rv64gc systemverilog-hdl

Created 2018-01-23

7,353 commits to master branch, last one 8 days ago

serv olofk

213

1.5k

isc

38

SERV - The SErial RISC-V CPU

asic fpga risc-v verilog

Created 2018-10-31

470 commits to main branch, last one 18 days ago

clash-compiler clash-lang

156

1.5k

other

53

Haskell to VHDL/Verilog/SystemVerilog compiler

asic fpga vhdl haskell verilog systemverilog hardware-description-language

Created 2013-07-04

6,103 commits to master branch, last one 3 days ago

OpenLane The-OpenROAD-Project

394

1.5k

apache-2.0

62

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

rtl asic vlsi 130nm magic yosys netgen caravel foundry klayout openram rtl2gds verilog openroad skywater soc-design system-on-chip

Created 2020-07-20

1,893 commits to master branch, last one 3 months ago

riscv ultraembedded

251

1.4k

bsd-3-clause

53

RISC-V CPU Core (RV32IM)

cpu asic fpga rv32i risc-v rv32im verilog verilator riscv-linux verification pipeline-processor

Created 2014-08-31

48 commits to master branch, last one 3 years ago

axi pulp-platform

282

1.2k

other

40

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

ip axi rtl asic axi4 fpga hardware axi4-lite systemverilog network-on-chip

Created 2018-04-12

1,323 commits to master branch, last one 15 days ago

biriscv ultraembedded

164

980

apache-2.0

32

32-bit Superscalar RISC-V CPU

cpu asic fpga linux rv32i risc-v rv32im xilinx artix-7 verilog coremark in-order verilator riscv-linux superscalar branch-prediction pipelined-processors

Created 2020-02-10

37 commits to master branch, last one 3 years ago

gemmini ucb-bar

189

914

other

30

Berkeley's Spatial Array Generator

dnn asic accelerator

Created 2018-10-31

820 commits to master branch, last one about a month ago

dss esig

386

861

lgpl-2.1

119

Digital Signature Service : creation, extension and validation of advanced electronic signatures

asic java cades jades pades xades signature esignature validation

Created 2015-01-30

6,565 commits to master branch, last one about a month ago

cores ultraembedded

221

769

unknown

49

Various HDL (Verilog) IP Cores

i2s rtl spi usb asic fpga sram uart audio sdram verilog verilator verilog-hdl verilog-components

Created 2015-05-30

54 commits to master branch, last one 3 years ago

vunit VUnit

271

768

other

50

VUnit is a unit testing framework for VHDL/SystemVerilog

asic fpga vhdl testbench verilog-hdl unit-testing verification systemverilog-hdl universal-verification-methodology

Created 2014-11-18

2,126 commits to master branch, last one about a month ago

Embedded-Neural-Network zssloth

120

557

unknown

90

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

asic fpga compression deep-learning neural-network

Created 2016-08-16

60 commits to master branch, last one about a year ago

ara pulp-platform

144

414

other

21

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

ara cpu rvv asic riscv vector rv64gcv

Created 2021-03-05

1,819 commits to main branch, last one 16 days ago

gf180mcu-pdk google

57

389

apache-2.0

21

PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

eda pdk asic 180nm gf180mcu openroad globalfoundries

Created 2022-07-20

112 commits to main branch, last one about a year ago

surf slaclab

69

382

other

48

A huge VHDL library for FPGA development

hdl asic fpga vhdl python firmware

Created 2016-08-23

7,930 commits to main branch, last one 5 days ago

rggen rggen

46

377

mit

14

Code generation tool for control and status registers

apb axi csr eda ral rtl soc uvm amba asic fpga vhdl verilog wishbone-bus systemverilog uvm-ral-model wiki-documents uvm-register-model register-descriptions

Created 2019-04-10

391 commits to master branch, last one about a month ago

tensil tensil-ai

30

375

other

10

Open source machine learning accelerators

hdl asic fpga scala silicon machine-learning artificial-intelligence

Created 2022-02-26

466 commits to main branch, last one 2 years ago

esp sld-columbia

119

363

other

25

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

asic fpga riscv accelerators system-on-chip network-on-chip embedded-systems

Created 2019-06-04

1,616 commits to main branch, last one 2 months ago

aes secworks

134

354

bsd-2-clause

26

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

aes asic fpga encryption block-cipher

Created 2014-02-21

693 commits to master branch, last one 2 days ago

async_fifo dpretet

83

321

other

11

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

cdc hdl asic fifo fpga async verilog synthesis verilator fifo-cache fifo-queue asic-design verilog-hdl verification icarus-verilog cross-clock-domain

Created 2017-03-28

49 commits to master branch, last one 11 months ago

awesome-dv troyguo

69

290

unknown

11

Awesome ASIC design verification

uvm asic verification asic-verification formal-verification

Created 2020-03-02

19 commits to master branch, last one 3 years ago

mempool pulp-platform

49

288

apache-2.0

8

A 256-RISC-V-core system with low-latency access into shared L1 memory.

asic risc-v manycore

Created 2019-11-21

1,572 commits to main branch, last one 2 months ago

openlane2 efabless

59

276

apache-2.0

13

The next generation of OpenLane, rewritten from scratch with a modular architecture

drc eda lvs pdk pnr sta asic flow vlsi flows gdsii sky130 silicon verilog gf180mcu openlane openroad rtl-to-gds

Created 2023-01-16

417 commits to main branch, last one about a month ago

systemrdl-compiler SystemRDL

70

250

mit

25

SystemRDL 2.0 language compiler front-end

csr eda asic fpga registers systemrdl design-automation systemrdl-compiler register-descriptions hardware-description-language register-description-language

Created 2018-03-11

590 commits to main branch, last one 27 days ago

cheshire pulp-platform

59

243

other

15

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

asic fpga riscv rtl-design simulation systemverilog

Created 2022-09-01

110 commits to main branch, last one a day ago

antminer-monitor anselal

144

233

gpl-3.0

34

Cryptocurrency ASIC mining hardware monitor using a simple web interface

asic dash avalon mining python bitcoin bitmain monitor antminer litecoin innosilicon hacktoberfest bitcoin-mining cryptocurrency mining-monitor antminer-monitor

Created 2017-09-25

212 commits to master branch, last one 2 years ago