Search Results - RepositoryStats

skywater-pdk google

375

2.9k

apache-2.0

150

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

eda pdk asic magic openram openroad skywater asic-library

Created 2020-05-06

370 commits to main branch, last one about a year ago

cva6 openhwgroup

652

2.1k

other

90

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

cpu asic fpga ariane risc-v rv64gc systemverilog-hdl

Created 2018-01-23

7,016 commits to master branch, last one 5 days ago

neorv32 stnolting

203

1.5k

bsd-3-clause

51

:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Created 2020-06-23

6,648 commits to main branch, last one 3 days ago

clash-compiler clash-lang

147

1.4k

other

57

Haskell to VHDL/Verilog/SystemVerilog compiler

asic fpga vhdl haskell verilog systemverilog hardware-description-language

Created 2013-07-04

5,983 commits to master branch, last one 5 days ago

serv olofk

176

1.3k

isc

37

SERV - The SErial RISC-V CPU

asic fpga risc-v verilog

Created 2018-10-31

435 commits to main branch, last one 10 days ago

OpenLane The-OpenROAD-Project

365

1.2k

apache-2.0

58

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

rtl asic vlsi 130nm magic yosys netgen caravel foundry klayout openram rtl2gds verilog openroad skywater soc-design system-on-chip

Created 2020-07-20

1,879 commits to master branch, last one 10 hours ago

riscv ultraembedded

214

1.1k

bsd-3-clause

50

RISC-V CPU Core (RV32IM)

cpu asic fpga rv32i risc-v rv32im verilog verilator riscv-linux verification pipeline-processor

Created 2014-08-31

48 commits to master branch, last one 2 years ago

axi pulp-platform

245

972

other

39

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

ip axi rtl asic axi4 fpga hardware axi4-lite systemverilog network-on-chip

Created 2018-04-12

1,248 commits to master branch, last one about a month ago

biriscv ultraembedded

139

798

apache-2.0

29

32-bit Superscalar RISC-V CPU

cpu asic fpga linux rv32i risc-v rv32im xilinx artix-7 verilog coremark in-order verilator riscv-linux superscalar branch-prediction pipelined-processors

Created 2020-02-10

37 commits to master branch, last one 2 years ago

dss esig

373

770

lgpl-2.1

112

Digital Signature Service : creation, extension and validation of advanced electronic signatures

asic java cades jades pades xades signature esignature validation

Created 2015-01-30

6,061 commits to master branch, last one 6 months ago

gemmini ucb-bar

144

711

other

29

Berkeley's Spatial Array Generator

dnn asic accelerator

Created 2018-10-31

736 commits to master branch, last one about a year ago

vunit VUnit

250

696

other

52

VUnit is a unit testing framework for VHDL/SystemVerilog

asic fpga vhdl testbench verilog-hdl unit-testing verification systemverilog-hdl universal-verification-methodology

Created 2014-11-18

2,064 commits to master branch, last one a day ago

cores ultraembedded

202

650

unknown

47

Various HDL (Verilog) IP Cores

i2s rtl spi usb asic fpga sram uart audio sdram verilog verilator verilog-hdl verilog-components

Created 2015-05-30

54 commits to master branch, last one 2 years ago

Embedded-Neural-Network zssloth

121

548

unknown

93

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

asic fpga compression deep-learning neural-network

Created 2016-08-16

60 commits to master branch, last one 4 months ago

gf180mcu-pdk google

53

351

apache-2.0

19

PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

eda pdk asic 180nm gf180mcu openroad globalfoundries

Created 2022-07-20

112 commits to main branch, last one about a year ago

tensil tensil-ai

27

346

other

9

Open source machine learning accelerators

hdl asic fpga scala silicon machine-learning artificial-intelligence

Created 2022-02-26

466 commits to main branch, last one about a year ago

ara pulp-platform

112

322

other

23

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

ara cpu rvv asic riscv vector rv64gcv

Created 2021-03-05

1,597 commits to main branch, last one a day ago

aes secworks

119

316

bsd-2-clause

27

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

aes asic fpga encryption block-cipher

Created 2014-02-21

682 commits to master branch, last one about a year ago

esp sld-columbia

101

310

other

25

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

asic fpga riscv accelerators system-on-chip network-on-chip embedded-systems

Created 2019-06-04

1,549 commits to main branch, last one 3 months ago

surf slaclab

51

298

other

47

A huge VHDL library for FPGA development

hdl asic fpga vhdl python firmware

Created 2016-08-23

7,505 commits to master branch, last one 6 days ago

rggen rggen

44

297

mit

13

Code generation tool for control and status registers

apb axi csr eda ral rtl soc uvm amba asic fpga vhdl verilog wishbone-bus systemverilog uvm-ral-model wiki-documents uvm-register-model register-descriptions

Created 2019-04-10

377 commits to master branch, last one 15 days ago

mempool pulp-platform

45

247

apache-2.0

8

A 256-RISC-V-core system with low-latency access into shared L1 memory.

asic risc-v manycore

Created 2019-11-21

1,511 commits to main branch, last one 6 days ago

antminer-monitor anselal

144

231

gpl-3.0

35

Cryptocurrency ASIC mining hardware monitor using a simple web interface

asic dash avalon mining python bitcoin bitmain monitor antminer litecoin innosilicon hacktoberfest bitcoin-mining cryptocurrency mining-monitor antminer-monitor

Created 2017-09-25

212 commits to master branch, last one about a year ago

awesome-dv troyguo

59

226

unknown

10

Awesome ASIC design verification

uvm asic verification asic-verification formal-verification

Created 2020-03-02

19 commits to master branch, last one 2 years ago

systemrdl-compiler SystemRDL

58

221

mit

25

SystemRDL 2.0 language compiler front-end

csr eda asic fpga registers systemrdl design-automation systemrdl-compiler register-descriptions hardware-description-language register-description-language

Created 2018-03-11

549 commits to main branch, last one about a month ago

async_fifo dpretet

70

220

other

10

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

cdc hdl asic fifo fpga async verilog synthesis verilator fifo-cache fifo-queue asic-design verilog-hdl verification icarus-verilog cross-clock-domain

Created 2017-03-28

49 commits to master branch, last one 2 months ago

livehd masc-ucsc

47

202

other

28

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

hdl asic fpga live lgraph synthesis simulation

Created 2018-04-23

6,507 commits to master branch, last one 6 days ago

open-register-design-tool Juniper

67

183

apache-2.0

43

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

eda uvm asic fpga jspec registers systemrdl systemverilog systemrdl-compiler register-descriptions

Created 2016-06-14

453 commits to master branch, last one 11 months ago

GDS3D trilomix

27

181

gpl-2.0

7

GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called proce...

eda fem asic mesh gdsii 3d-models integrated-circuits

Created 2017-01-26

42 commits to master branch, last one 8 days ago

hiveos-asic minershive

74

171

other

31

Hive OS client for ASICs

asic mining bitcoin litecoin

Created 2018-04-02

1,544 commits to master branch, last one about a year ago