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mit

Code generation tool for control and status registers

apb axi csr eda ral rtl soc uvm amba asic fpga vhdl verilog wishbone-bus systemverilog uvm-ral-model wiki-documents uvm-register-model register-descriptions

Created 2019-04-10

382 commits to master branch, last one 5 days ago

gpl-3.0

Generate UVM register model from compiled SystemRDL input

eda uvm asic fpga registers uvm-ral-model uvm-register-model

Created 2019-08-23

47 commits to main branch, last one about a year ago