10 results found Sort:

ZipCPU
zipcpu ZipCPU
163
1.4k
unknown
63
A small, light weight, RISC CPU soft core
cpu fpga zipcpu verilog risc-cpu wishbone soft-core verilator wishbone-bus cross-compiler
Created 2016-09-21
820 commits to master branch, last one about a month ago
ZipCPU
wb2axip ZipCPU
107
527
unknown
30
Bus bridges and other odds and ends
fpga gplv3 xilinx axi-bus wishbone wishbone-bus xilinx-vivado
Created 2016-09-21
499 commits to master branch, last one about a month ago
rggen
rggen rggen
46
375
mit
14
Code generation tool for control and status registers
apb axi csr eda ral rtl soc uvm amba asic fpga vhdl verilog wishbone-bus systemverilog uvm-ral-model wiki-documents uvm-register-model register-descriptions
Created 2019-04-10
391 commits to master branch, last one about a month ago
ZipCPU
wbuart32 ZipCPU
48
296
gpl-3.0
15
A simple, basic, formally verified UART controller
fpga uart verilog wishbone verilator serialport uart-verilog wishbone-bus
Created 2016-09-21
160 commits to master branch, last one about a year ago
ZipCPU
sdspi ZipCPU
41
254
unknown
10
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
axi emmc fpga sdio sd-card verilog wishbone verilator sd-interface wishbone-bus spi-interface verilog-components
Created 2016-09-21
273 commits to master branch, last one 2 months ago
ZipCPU
autofpga ZipCPU
20
175
gpl-3.0
17
A utility for Composing FPGA designs from Peripherals
fpga verilog wishbone verilator c-plus-plus wishbone-bus
Created 2017-03-29
304 commits to master branch, last one 3 months ago
ZipCPU
openarty ZipCPU
24
128
unknown
14
An Open Source configuration of the Arty platform
arty fpga zipcpu fpga-soc wishbone verilator wishbone-bus
Created 2016-09-26
398 commits to master branch, last one 4 years ago
jakubcabal
uart-for-fpga jakubcabal
28
95
mit
10
Simple UART controller for FPGA written in VHDL
fpga ghdl uart vhdl cyc1000 wishbone controller simulation wishbone-bus uart-loopback uart-controller
Created 2015-07-24
62 commits to master branch, last one 3 years ago
ZipCPU
wbscope ZipCPU
6
77
unknown
8
A wishbone controlled scope for FPGA's
fpga verilog wishbone verilator wishbone-bus debugging-tools
Created 2016-09-21
50 commits to master branch, last one about a year ago
lxp32
lxp32-cpu lxp32
14
60
mit
4
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
cpu fpga risc vhdl assembly risc-cpu wishbone assembler soft-core wishbone-bus risc-processor
Created 2016-02-20
151 commits to develop branch, last one 3 months ago