16 results found Sort:

mortbopet
Ripes mortbopet
267
2.4k
mit
45
A graphical processor simulator and assembly editor for the RISC-V ISA
qt risc risc-v education simulator cpu-emulator computer-architecture processor-architecture
Created 2017-10-27
1,534 commits to master branch, last one about a month ago
LekKit
RVVM LekKit
55
826
gpl-3.0
21
The RISC-V Virtual Machine
c vm jit risc rvvm linux riscv risc-v riscv32 riscv64 emulator emulation emulators riscv-linux tracing-jit translation riscv-emulator riscv-simulator virtual-machine instruction-decoding
Created 2021-02-16
1,339 commits to staging branch, last one 23 days ago
chipsalliance
Cores-VeeR-EH1 chipsalliance
207
779
apache-2.0
57
VeeR EH1 core
rtl axi4 fpga risc veer riscv risc-v fusesoc riscv32 ahb-lite processor verilator asic-design western-digital open-source-hardware
Created 2019-06-02
125 commits to main branch, last one about a year ago
michaeljclark
rv8 michaeljclark
97
662
mit
44
RISC-V simulator for x86-64
isa rv8 risc linux riscv rv-jit rv-sim rv-sys rv-meta emulator metadata histogram simulator disassembler macro-op-fusion binary-translation
Created 2016-01-30
2,279 commits to master branch, last one 5 years ago
andrescv
jupiter andrescv
35
408
gpl-3.0
12
RISC-V Assembler and Runtime Simulator
asm risc rv32 riscv rv32g risc-v runtime assembler education simulator riscv-simulator runtime-simulator
Created 2017-12-23
929 commits to main branch, last one 4 years ago
Wren6991
RISCBoy Wren6991
10
227
unknown
18
Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink
cpu pcb fpga risc risc-v gameboy
Created 2018-03-16
734 commits to master branch, last one 11 months ago
kvakil
venus kvakil
50
179
mit
6
RISC-V instruction set simulator built for education
risc risc-v assembler education
Created 2017-07-08
648 commits to master branch, last one 5 years ago
Mariotti94
WebRISC-V Mariotti94
11
112
bsd-3-clause
7
WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]
php risc risc-v assembly pipeline education simulator computer-architecture processor-architecture pipeline-simulation-environment
Created 2019-09-21
47 commits to master branch, last one 4 months ago
vmmc2
Vulcan vmmc2
10
101
mit
9
RISC-V Instruction Set Simulator (Built for education).
risc risc-v assembly education simulator computer-architecture
Created 2020-05-01
577 commits to master branch, last one 2 years ago
mrisc32
mrisc32 mrisc32
9
90
cc-by-sa-4.0
9
MRSIC32 ISA documentation and development
cpu isa risc mrisc32
This repository has been archived (exclude archived)
Created 2018-01-03
939 commits to master branch, last one 9 months ago
AluVM
rust-aluvm AluVM
22
58
apache-2.0
9
Rust implementation of AluVM (RISC functional machine)
risc rust blockchain edge-computing smart-contracts virtual-machine embedded-systems microcontrollers functional-programming instruction-set-architecture
Created 2021-03-28
510 commits to master branch, last one 7 days ago
lxp32
lxp32-cpu lxp32
13
56
mit
5
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
cpu fpga risc vhdl assembly risc-cpu wishbone assembler soft-core wishbone-bus risc-processor
Created 2016-02-20
140 commits to develop branch, last one about a year ago
edson-acordi
4bit-microcomputer edson-acordi
2
53
other
5
MikroLeo project files (schematic, PCB, assembler, emulator/debugger, circuit simulation file, documentation, example of programs etc). MikroLeo is a 4-bit microcomputer developed mainly for education...
alu asm cpu oshw risc 4-bit nibble 74hctxxx computer didactic assembler education logic-gates open-source programming microcomputer assembly-language digital-electronics harvard-architecture
Created 2020-01-18
328 commits to master branch, last one 3 months ago
fzipp
oberon fzipp
4
49
isc
2
Project Oberon RISC emulator in Go
go risc wirth golang oberon emulator oberon-07 wirth-oberon oberon-system project-oberon
Created 2021-07-21
110 commits to main branch, last one 11 days ago
openid
sharedsignals openid
11
41
unknown
22
OpenID Shared Signals Working Group Repository
ssf caep risc sharedsignals
Created 2022-01-25
271 commits to main branch, last one 5 days ago
ben-marshall
croyde-riscv ben-marshall
4
41
mit
2
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
cpu risc yosys crypto risc-v riscv64 verilog verilator mit-license cryptography systemverilog microcontroller micro-controller formal-verification
Created 2020-03-30
409 commits to master branch, last one 2 years ago