ben-marshall / croyde-riscv

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

Date Created 2020-03-30 (4 years ago)

Commits 409 (last one 2 years ago)

Stargazers 42 (0 this week)

Watchers 3 (0 this week)

Forks 5

License mit

Ranking

RepositoryStats indexes 534,880 repositories, of these ben-marshall/croyde-riscv is ranked #467,781 (13th percentile) for total stargazers, and #399,187 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #128/154.

ben-marshall/croyde-riscv is also tagged with popular topics, for these it's ranked: cryptography (#880/950), crypto (#633/749), verilog (#238/257), risc-v (#200/226), microcontroller (#180/187)

Other Information

ben-marshall/croyde-riscv has Github issues enabled, there are 3 open issues and 0 closed issues.

All Topics

cpu risc yosys crypto risc-v riscv64 verilog verilator mit-license cryptography systemverilog microcontroller micro-controller formal-verification

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1 commits on the default branch (master) since jan '22

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The primary language is SystemVerilog but there's also others...

updated: 2024-06-16 @ 04:15am, id: 251418791 / R_kgDODvxYpw