29 results found Sort:

verilator
verilator verilator
653
2.8k
lgpl-3.0
72
Verilator open-source SystemVerilog simulator and lint system
cpp rtl systemc verilog compilers verilator system-verilog verilog-simulator
Created 2019-06-13
7,810 commits to master branch, last one 4 hours ago
ultraembedded
riscv ultraembedded
252
1.4k
bsd-3-clause
53
RISC-V CPU Core (RV32IM)
cpu asic fpga rv32i risc-v rv32im verilog verilator riscv-linux verification pipeline-processor
Created 2014-08-31
48 commits to master branch, last one 3 years ago
ZipCPU
zipcpu ZipCPU
164
1.4k
unknown
63
A small, light weight, RISC CPU soft core
cpu fpga zipcpu verilog risc-cpu wishbone soft-core verilator wishbone-bus cross-compiler
Created 2016-09-21
820 commits to master branch, last one 2 months ago
ultraembedded
biriscv ultraembedded
165
993
apache-2.0
32
32-bit Superscalar RISC-V CPU
cpu asic fpga linux rv32i risc-v rv32im xilinx artix-7 verilog coremark in-order verilator riscv-linux superscalar branch-prediction pipelined-processors
Created 2020-02-10
37 commits to master branch, last one 3 years ago
chipsalliance
Cores-VeeR-EH1 chipsalliance
228
868
apache-2.0
57
VeeR EH1 core
rtl axi4 fpga risc veer riscv risc-v fusesoc riscv32 ahb-lite processor verilator asic-design western-digital open-source-hardware
Created 2019-06-02
125 commits to main branch, last one 2 years ago
ultraembedded
cores ultraembedded
221
773
unknown
49
Various HDL (Verilog) IP Cores
i2s rtl spi usb asic fpga sram uart audio sdram verilog verilator verilog-hdl verilog-components
Created 2015-05-30
54 commits to master branch, last one 3 years ago
olofk
edalize olofk
200
681
bsd-2-clause
31
An abstraction library for interfacing EDA tools
eda fpga ghdl vhdl fossi yosys altera vivado xilinx lattice verilog icestorm modelsim spyglass synthesis verilator simulation riviera-pro systemverilog icarus-verilog
Created 2018-05-09
569 commits to main branch, last one 18 days ago
dpretet
async_fifo dpretet
83
323
other
11
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
cdc hdl asic fifo fpga async verilog synthesis verilator fifo-cache fifo-queue asic-design verilog-hdl verification icarus-verilog cross-clock-domain
Created 2017-03-28
49 commits to master branch, last one 12 months ago
mshr-h
vscode-verilog-hdl-support mshr-h
83
318
mit
11
HDL support for VS Code
svls ctags vivado vscode verilog iverilog modelsim verilator verilog-hdl hacktoberfest systemverilog icarus-verilog systemverilog-support bluespec-systemverilog language-server-client
Created 2015-12-10
566 commits to main branch, last one about a month ago
ZipCPU
wbuart32 ZipCPU
49
299
gpl-3.0
16
A simple, basic, formally verified UART controller
fpga uart verilog wishbone verilator serialport uart-verilog wishbone-bus
Created 2016-09-21
160 commits to master branch, last one about a year ago
chipsalliance
Cores-VeeR-EL2 chipsalliance
82
273
apache-2.0
26
VeeR EL2 Core
el2 rtl axi4 fpga riscv risc-v fusesoc riscv32 ahb-lite processor verilator asic-design western-digital open-source-hardware
Created 2020-01-09
1,151 commits to main branch, last one 10 days ago
ZipCPU
sdspi ZipCPU
43
270
unknown
11
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
axi emmc fpga sdio sd-card verilog wishbone verilator sd-interface wishbone-bus spi-interface verilog-components
Created 2016-09-21
273 commits to master branch, last one 3 months ago
ZipCPU
dblclockfft ZipCPU
39
236
unknown
14
A configurable C++ generator of pipelined Verilog FFT cores
fft fpga gplv3 verilog verilator verilog-components
Created 2016-09-21
109 commits to master branch, last one about a year ago
ZipCPU
autofpga ZipCPU
20
176
gpl-3.0
17
A utility for Composing FPGA designs from Peripherals
fpga verilog wishbone verilator c-plus-plus wishbone-bus
Created 2017-03-29
304 commits to master branch, last one 3 months ago
ZipCPU
vgasim ZipCPU
20
165
unknown
15
A Video display simulator
vga fpga gplv3 gtkmm video verilog verilator video-simulator
Created 2017-12-27
43 commits to master branch, last one 9 months ago
ZipCPU
openarty ZipCPU
24
129
unknown
14
An Open Source configuration of the Arty platform
arty fpga zipcpu fpga-soc wishbone verilator wishbone-bus
Created 2016-09-26
398 commits to master branch, last one 4 years ago
ZipCPU
dpll ZipCPU
27
105
unknown
10
A collection of phase locked loop (PLL) related projects
pll fpga gplv3 verilog verilator
Created 2017-12-04
26 commits to master branch, last one about a year ago
ZipCPU
wbscope ZipCPU
6
80
unknown
8
A wishbone controlled scope for FPGA's
fpga verilog wishbone verilator wishbone-bus debugging-tools
Created 2016-09-21
50 commits to master branch, last one about a year ago
dpretet
svut dpretet
17
77
mit
3
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
tdd vcd flow foss svut python surfer gtkwave verilog testcase simulator verilator simulation mit-license systemverilog tdd-utilities icarus-verilog verification-methodologies
Created 2017-03-12
195 commits to master branch, last one 5 months ago
chili-chips-ba
wireguard-fpga chili-chips-ba
0
76
bsd-3-clause
10
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...
iss rtl vpn fpga vproc cocotb risc-v verilog embedded verilator wireguard
Created 2024-07-13
238 commits to main branch, last one 13 days ago
ZipCPU
interpolation ZipCPU
13
60
unknown
5
Digital Interpolation Techniques Applied to Digital Signal Processing
dsp fpga verilog verilator interpolation interpolation-methods interpolation-techniques
Created 2017-03-25
21 commits to master branch, last one 9 months ago
FDUCSLG
ICS-2021Spring-FDU FDUCSLG
17
50
gpl-3.0
2
Introduction to Computer Systems (II), Spring 2021
fpga mips nscscc vivado verilator systemverilog
Created 2021-02-27
45 commits to master branch, last one 3 years ago
tscheipel
HaDes-V tscheipel
2
46
mit
1
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...
riscv rv32i risc-v vivado gtkwave pipelines verilator c-programming systemverilog open-education system-verilog processor-design university-course assembly-programming computer-architecture microcontroller-design processor-architecture hardware-software-codesign open-educational-resources
Created 2024-12-14
4 commits to main branch, last one 2 months ago
fredrequin
verilator_xilinx fredrequin
5
45
bsd-2-clause
3
Re-coded Xilinx primitives for Verilator use
fpga verilog verilator xilinx-fpga
Created 2020-10-13
21 commits to main branch, last one about a year ago
ben-marshall
croyde-riscv ben-marshall
7
44
mit
2
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
cpu risc yosys crypto risc-v riscv64 verilog verilator mit-license cryptography systemverilog microcontroller micro-controller formal-verification
Created 2020-03-30
409 commits to master branch, last one 3 years ago
vmunoz82
eda_tools vmunoz82
7
43
mit
2
A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator...
z3 eda gowin yosys nmigen silice yices2 amaranth boolector verilator dockerfile symbiyosys nextpnr-ecp5 nextpnr-ice40 openfpgaloader
Created 2020-12-07
10 commits to main branch, last one about a year ago
ethanuppal
marlin ethanuppal
3
42
mpl-2.0
1
🦀 No nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl
rust testing verilog hardware testbench verilator simulation
Created 2025-01-05
112 commits to main branch, last one 13 days ago
dbhi
vboard dbhi
7
41
unknown
5
Virtual development board for HDL design
fli hdl vpi ghdl vhdl cosim verilog verilator vhpidirect
Created 2020-04-30
47 commits to main branch, last one 2 years ago
microdynamics-cpu
tree-core-cpu microdynamics-cpu
3
38
gpl-3.0
5
:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and v...
cpu rtl riscv scala chisel softcore processor rt-thread verilator
Created 2021-01-02
689 commits to main branch, last one about a year ago