21 results found Sort:

verilator
verilator verilator
544
2.2k
lgpl-3.0
74
Verilator open-source SystemVerilog simulator and lint system
cpp rtl systemc verilog compilers verilator system-verilog verilog-simulator
Created 2019-06-13
6,963 commits to master branch, last one a day ago
ZipCPU
zipcpu ZipCPU
150
1.2k
unknown
61
A small, light weight, RISC CPU soft core
cpu fpga zipcpu verilog risc-cpu wishbone soft-core verilator wishbone-bus cross-compiler
Created 2016-09-21
790 commits to master branch, last one 10 days ago
ultraembedded
riscv ultraembedded
209
1.1k
bsd-3-clause
48
RISC-V CPU Core (RV32IM)
cpu asic fpga rv32i risc-v rv32im verilog verilator riscv-linux verification pipeline-processor
Created 2014-08-31
48 commits to master branch, last one 2 years ago
ultraembedded
biriscv ultraembedded
134
785
apache-2.0
27
32-bit Superscalar RISC-V CPU
cpu asic fpga linux rv32i risc-v rv32im xilinx artix-7 verilog coremark in-order verilator riscv-linux superscalar branch-prediction pipelined-processors
Created 2020-02-10
37 commits to master branch, last one 2 years ago
chipsalliance
Cores-VeeR-EH1 chipsalliance
207
779
apache-2.0
57
VeeR EH1 core
rtl axi4 fpga risc veer riscv risc-v fusesoc riscv32 ahb-lite processor verilator asic-design western-digital open-source-hardware
Created 2019-06-02
125 commits to main branch, last one about a year ago
ultraembedded
cores ultraembedded
199
645
unknown
47
Various HDL (Verilog) IP Cores
i2s rtl spi usb asic fpga sram uart audio sdram verilog verilator verilog-hdl verilog-components
Created 2015-05-30
54 commits to master branch, last one 2 years ago
olofk
edalize olofk
180
597
bsd-2-clause
33
An abstraction library for interfacing EDA tools
eda fpga ghdl vhdl fossi yosys altera vivado xilinx lattice verilog icestorm modelsim spyglass synthesis verilator simulation riviera-pro systemverilog icarus-verilog
Created 2018-05-09
523 commits to main branch, last one 14 days ago
mshr-h
vscode-verilog-hdl-support mshr-h
75
282
mit
9
HDL support for VS Code
svls ctags vivado vscode verilog iverilog modelsim verilator verilog-hdl hacktoberfest systemverilog icarus-verilog systemverilog-support bluespec-systemverilog language-server-client
Created 2015-12-10
535 commits to main branch, last one about a month ago
ZipCPU
wbuart32 ZipCPU
48
257
gpl-3.0
15
A simple, basic, formally verified UART controller
fpga uart verilog wishbone verilator serialport uart-verilog wishbone-bus
Created 2016-09-21
160 commits to master branch, last one 4 months ago
chipsalliance
Cores-VeeR-EL2 chipsalliance
67
224
apache-2.0
24
VeeR EL2 Core
el2 rtl axi4 fpga riscv risc-v fusesoc riscv32 ahb-lite processor verilator asic-design western-digital open-source-hardware
Created 2020-01-09
372 commits to main branch, last one a day ago
dpretet
async_fifo dpretet
68
213
other
10
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
cdc hdl asic fifo fpga async verilog synthesis verilator fifo-cache fifo-queue asic-design verilog-hdl verification icarus-verilog cross-clock-domain
Created 2017-03-28
49 commits to master branch, last one about a month ago
ZipCPU
dblclockfft ZipCPU
28
208
unknown
14
A configurable C++ generator of pipelined Verilog FFT cores
fft fpga gplv3 verilog verilator verilog-components
Created 2016-09-21
109 commits to master branch, last one about a month ago
ZipCPU
autofpga ZipCPU
18
157
gpl-3.0
18
A utility for Composing FPGA designs from Peripherals
fpga verilog wishbone verilator c-plus-plus wishbone-bus
Created 2017-03-29
301 commits to master branch, last one 4 months ago
ZipCPU
vgasim ZipCPU
15
150
unknown
15
A Video display simulator
vga fpga gplv3 gtkmm video verilog verilator video-simulator
Created 2017-12-27
40 commits to master branch, last one about a year ago
ZipCPU
sdspi ZipCPU
25
149
unknown
9
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
axi emmc fpga sdio sd-card verilog wishbone verilator sd-interface wishbone-bus spi-interface verilog-components
Created 2016-09-21
187 commits to master branch, last one 9 days ago
ZipCPU
openarty ZipCPU
24
116
unknown
14
An Open Source configuration of the Arty platform
arty fpga zipcpu fpga-soc wishbone verilator wishbone-bus
Created 2016-09-26
398 commits to master branch, last one 3 years ago
ZipCPU
dpll ZipCPU
26
91
unknown
10
A collection of phase locked loop (PLL) related projects
pll fpga gplv3 verilog verilator
Created 2017-12-04
26 commits to master branch, last one 4 months ago
ZipCPU
wbscope ZipCPU
6
70
unknown
9
A wishbone controlled scope for FPGA's
fpga verilog wishbone verilator wishbone-bus debugging-tools
Created 2016-09-21
50 commits to master branch, last one 4 months ago
dpretet
svut dpretet
14
62
mit
3
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
tdd vcd flow foss svut python gtkwave verilog testcase simulator verilator simulation mit-license systemverilog tdd-utilities icarus-verilog verification-methodologies
Created 2017-03-12
171 commits to master branch, last one about a year ago
FDUCSLG
ICS-2021Spring-FDU FDUCSLG
19
43
gpl-3.0
3
Introduction to Computer Systems (II), Spring 2021
fpga mips nscscc vivado verilator systemverilog
Created 2021-02-27
45 commits to master branch, last one 2 years ago
ben-marshall
croyde-riscv ben-marshall
4
41
mit
2
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
cpu risc yosys crypto risc-v riscv64 verilog verilator mit-license cryptography systemverilog microcontroller micro-controller formal-verification
Created 2020-03-30
409 commits to master branch, last one 2 years ago