fredrequin / verilator_xilinx

Re-coded Xilinx primitives for Verilator use

Date Created 2020-10-13 (4 years ago)

Commits 21 (last one about a year ago)

Stargazers 41 (0 this week)

Watchers 4 (0 this week)

Forks 3

License bsd-2-clause

Ranking

RepositoryStats indexes 595,856 repositories, of these fredrequin/verilator_xilinx is ranked #515,470 (13th percentile) for total stargazers, and #377,401 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #472/563.

fredrequin/verilator_xilinx is also tagged with popular topics, for these it's ranked: fpga (#444/488), verilog (#264/289)

Other Information

fredrequin/verilator_xilinx has Github issues enabled, there is 1 open issue and 0 closed issues.

All Topics

fpga verilog verilator xilinx-fpga

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

11 commits on the default branch (main) since jan '22

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Issue History

Languages

The only known language in this repository is Verilog

updated: 2024-10-28 @ 09:29pm, id: 303693183 / R_kgDOEhn9fw