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open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
Created
2019-11-08
812 commits to master branch, last one about a month ago
Documenting the Xilinx 7-series bit-stream format.
Created
2017-12-16
3,866 commits to master branch, last one 6 days ago
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Created
2017-11-16
5,212 commits to main branch, last one 11 days ago
Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.
Created
2020-09-04
362 commits to master branch, last one 28 days ago
blaze is a Rust library for ZK acceleration on Xilinx FPGAs.
Created
2022-09-04
14 commits to main branch, last one 9 months ago
SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
Created
2019-04-01
461,606 commits to sycl/unified/master branch, last one 6 months ago
Xilinx Virtual Cable Server for Raspberry Pi
Created
2017-04-19
9 commits to master branch, last one 2 years ago
Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
Created
2021-06-20
5 commits to main branch, last one 2 years ago
Plugins for Yosys developed as part of the F4PGA project.
Created
2019-11-07
1,466 commits to main branch, last one 4 months ago
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
Created
2020-07-15
28 commits to master branch, last one 2 years ago