21 results found Sort:

The-OpenROAD-Project
OpenLane The-OpenROAD-Project
359
1.2k
apache-2.0
58
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
rtl asic vlsi 130nm magic yosys netgen caravel foundry klayout openram rtl2gds verilog openroad skywater soc-design system-on-chip
Created 2020-07-20
1,877 commits to master branch, last one 4 days ago
cariboulabs
cariboulite cariboulabs
93
1.0k
unknown
58
CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR
pi rf rpi sdr fpga ice40 radio yosys defined icestorm software raspberry
Created 2021-06-13
406 commits to main branch, last one about a month ago
m-labs
nmigen m-labs
55
644
other
51
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
hdl fpga yosys nmigen
Created 2018-12-08
829 commits to master branch, last one 2 years ago
olofk
edalize olofk
180
597
bsd-2-clause
33
An abstraction library for interfacing EDA tools
eda fpga ghdl vhdl fossi yosys altera vivado xilinx lattice verilog icestorm modelsim spyglass synthesis verilator simulation riviera-pro systemverilog icarus-verilog
Created 2018-05-09
523 commits to main branch, last one 14 days ago
nturley
netlistsvg nturley
75
590
mit
24
draws an SVG schematic from a JSON netlist
elk yosys klayjs diagram netlist visualization
Created 2016-11-30
245 commits to master branch, last one 4 months ago
zachjs
sv2v zachjs
49
485
bsd-3-clause
15
SystemVerilog to Verilog conversion
yosys verilog conversion systemverilog
Created 2019-02-08
1,005 commits to master branch, last one 23 days ago
efabless
caravel efabless
63
257
apache-2.0
19
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
magic yosys sky130 caravel openram openroad picorv32 vexriscv
Created 2021-10-07
1,592 commits to main branch, last one a day ago
apfelaudio
eurorack-pmod apfelaudio
8
164
other
6
A eurorack-friendly audio frontend compatible with many FPGA boards.
fpga pmod kicad yosys cocotb verilog eurorack hardware electronics synthesizer modular-synthesizers
Created 2022-06-18
198 commits to master branch, last one 2 months ago
efabless
caravel_mpw-one efabless
134
135
apache-2.0
17
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
magic yosys sky130 caravel openram openroad picorv32
Created 2020-11-12
1,100 commits to master branch, last one 2 years ago
chipsalliance
fpga-tool-perf chipsalliance
28
97
apache-2.0
16
FPGA tool performance profiling
vpr fpga perf f4pga yosys nextpnr symbiflow toolchain arachne-pnr conda-environment performance-analysis
Created 2018-06-22
1,187 commits to main branch, last one 9 months ago
scarv
xcrypto scarv
10
88
mit
13
XCrypto: a cryptographic ISE for RISC-V
cpu ise riscv yosys crypto risc-v verilog xcrypto hardware mit-license open-source cryptography icarus-verilog research-project formal-verification hardware-acceleration instruction-set-architecture
This repository has been archived (exclude archived)
Created 2018-07-30
874 commits to master branch, last one about a year ago
ECP5-PCIe
ECP5-PCIe ECP5-PCIe
5
87
unknown
19
Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
ecp5 fpga pcie yosys nextpnr trellis amaranth gateware prjtrellis pcie-interface
Created 2020-05-12
114 commits to x4PathWidth branch, last one about a year ago
chipsalliance
yosys-f4pga-plugins chipsalliance
46
82
apache-2.0
18
Plugins for Yosys developed as part of the F4PGA project.
eda fpga f4pga yosys xilinx toolchain xilinx-fpga yosys-plugin
Created 2019-11-07
1,466 commits to main branch, last one 4 months ago
PyFPGA
pyfpga PyFPGA
7
77
gpl-3.0
4
A Python package to use FPGA development tools programmatically.
amd ise tcl fpga ghdl actel intel yosys altera libero python vivado xilinx lattice nextpnr quartus trellis icestorm microchip microsemi
Created 2021-02-10
502 commits to main branch, last one 2 years ago
lushaylabs
tangnano9k-series-examples lushaylabs
15
68
unknown
4
Examples for the Lushay Labs tang nano 9k series
fpga yosys apicula nextpnr tangnano9k
Created 2022-08-13
34 commits to master branch, last one 2 months ago
YoWASP
yosys YoWASP
2
63
isc
4
Unofficial Yosys WebAssembly packages
fpga pypi yosys python yowasp webassembly
Created 2020-06-23
730 commits to develop branch, last one a day ago
tmeissner
psl_with_ghdl tmeissner
3
60
lgpl-3.0
11
Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
psl ghdl vhdl yosys assertions symbiyosys formal-verification functional-coverage
Created 2020-05-02
114 commits to master branch, last one about a year ago
multigcs
LinuxCNC-RIO multigcs
17
60
gpl-2.0
18
RealtimeIO for LinuxCNC based on an FPGA
ecp5 fpga ice40 yosys nextpnr icestorm linuxcnc tangnano9k linuxcnc-fpga
Created 2023-05-15
628 commits to main branch, last one 4 months ago
stnolting
neorv32-setups stnolting
15
54
bsd-3-clause
8
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
soc fpga ghdl vhdl intel yosys risc-v xilinx lattice neorv32 verilog
Created 2022-01-11
414 commits to main branch, last one 4 days ago
SymbiFlow
sphinxcontrib-hdl-diagrams SymbiFlow
17
52
apache-2.0
16
Sphinx Extension which generates various types of diagrams from Verilog code.
hdl rtl fpga yosys sphinx verilog diagrams symbiflow documentation sphinx-extension documentation-tool
Created 2019-10-01
171 commits to main branch, last one 8 months ago
ben-marshall
croyde-riscv ben-marshall
4
41
mit
2
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
cpu risc yosys crypto risc-v riscv64 verilog verilator mit-license cryptography systemverilog microcontroller micro-controller formal-verification
Created 2020-03-30
409 commits to master branch, last one 2 years ago