13 results found Sort:

ghdl
ghdl ghdl
380
2.5k
gpl-2.0
100
VHDL 2008/93/87 simulator
gcc ghdl llvm vhdl compiler hardware simulator testbench hacktoberfest
Created 2015-11-18
10,004 commits to master branch, last one 2 days ago
olofk
edalize olofk
199
671
bsd-2-clause
31
An abstraction library for interfacing EDA tools
eda fpga ghdl vhdl fossi yosys altera vivado xilinx lattice verilog icestorm modelsim spyglass synthesis verilator simulation riviera-pro systemverilog icarus-verilog
Created 2018-05-09
566 commits to main branch, last one 27 days ago
suoto
hdl_checker suoto
25
205
gpl-3.0
16
Repurposing existing HDL tools to help writing better code
hdl vim ghdl vhdl python xilinx verilog vim-ale coc-nvim modelsim emacs-lsp questasim lsp-server hdl-checker mentor-msim systemverilog xilinx-vivado syntax-checker language-server vivado-simulator
Created 2016-01-23
390 commits to master branch, last one 3 years ago
jakubcabal
spi-fpga jakubcabal
41
173
mit
15
SPI master and SPI slave for FPGA written in VHDL
spi fpga ghdl vhdl cyc1000 spi-slave controller spi-master spi-loopback accelerometer spi-controller
Created 2016-07-03
41 commits to master branch, last one 3 years ago
PyFPGA
pyfpga PyFPGA
15
125
gpl-3.0
3
A Python package to use FPGA development tools programmatically.
ise tcl fpga ghdl yosys libero python vivado diamond nextpnr quartus trellis icestorm
Created 2021-02-10
796 commits to main branch, last one 12 days ago
jakubcabal
uart-for-fpga jakubcabal
28
98
mit
10
Simple UART controller for FPGA written in VHDL
fpga ghdl uart vhdl cyc1000 wishbone controller simulation wishbone-bus uart-loopback uart-controller
Created 2015-07-24
62 commits to master branch, last one 3 years ago
Paebbels
JSON-for-VHDL Paebbels
17
78
other
13
A JSON library implemented in VHDL.
fpga ghdl json vhdl parser xilinx lattice modelsim questasim synthesis fileformat simulation
Created 2015-09-01
61 commits to master branch, last one 2 years ago
stnolting
neorv32-verilog stnolting
18
78
bsd-3-clause
9
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
asic fpga ghdl neorv32 verilog icarus-verilog
Created 2022-08-27
383 commits to main branch, last one 3 days ago
stnolting
neorv32-setups stnolting
21
72
bsd-3-clause
8
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
soc fpga ghdl vhdl intel yosys risc-v xilinx lattice neorv32 verilog
Created 2022-01-11
574 commits to main branch, last one 3 days ago
tmeissner
psl_with_ghdl tmeissner
5
66
lgpl-3.0
10
Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
psl ghdl vhdl yosys assertions symbiyosys formal-verification functional-coverage
Created 2020-05-02
115 commits to master branch, last one 2 months ago
mnemocron
my-discrete-fpga mnemocron
2
42
gpl-3.0
3
My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.
7400 fpga ghdl vhdl fpga-soc breadboard-computer
Created 2023-09-04
93 commits to main branch, last one 11 months ago
dbhi
vboard dbhi
7
41
unknown
5
Virtual development board for HDL design
fli hdl vpi ghdl vhdl cosim verilog verilator vhpidirect
Created 2020-04-30
47 commits to main branch, last one 2 years ago
stnolting
neorv32-riscof stnolting
8
32
bsd-3-clause
5
✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
isa ghdl vhdl riscv risc-v riscof neorv32 processor sail-riscv verification
Created 2022-09-18
851 commits to main branch, last one 3 days ago