11 results found Sort:

ghdl
ghdl ghdl
370
2.4k
gpl-2.0
100
VHDL 2008/93/87 simulator
gcc ghdl llvm vhdl compiler hardware simulator testbench hacktoberfest
Created 2015-11-18
9,794 commits to master branch, last one 2 days ago
olofk
edalize olofk
193
650
bsd-2-clause
33
An abstraction library for interfacing EDA tools
eda fpga ghdl vhdl fossi yosys altera vivado xilinx lattice verilog icestorm modelsim spyglass synthesis verilator simulation riviera-pro systemverilog icarus-verilog
Created 2018-05-09
549 commits to main branch, last one 15 days ago
suoto
hdl_checker suoto
23
195
gpl-3.0
17
Repurposing existing HDL tools to help writing better code
hdl vim ghdl vhdl python xilinx verilog vim-ale coc-nvim modelsim emacs-lsp questasim lsp-server hdl-checker mentor-msim systemverilog xilinx-vivado syntax-checker language-server vivado-simulator
Created 2016-01-23
390 commits to master branch, last one 2 years ago
jakubcabal
spi-fpga jakubcabal
40
168
mit
16
SPI master and SPI slave for FPGA written in VHDL
spi fpga ghdl vhdl cyc1000 spi-slave controller spi-master spi-loopback accelerometer spi-controller
Created 2016-07-03
41 commits to master branch, last one 3 years ago
PyFPGA
pyfpga PyFPGA
10
94
gpl-3.0
3
A Python package to use FPGA development tools programmatically.
amd ise tcl fpga ghdl actel intel yosys altera libero python vivado xilinx lattice nextpnr quartus trellis icestorm microchip microsemi
Created 2021-02-10
502 commits to main branch, last one 2 years ago
jakubcabal
uart-for-fpga jakubcabal
27
92
mit
11
Simple UART controller for FPGA written in VHDL
fpga ghdl uart vhdl cyc1000 wishbone controller simulation wishbone-bus uart-loopback uart-controller
Created 2015-07-24
62 commits to master branch, last one 3 years ago
Paebbels
JSON-for-VHDL Paebbels
16
76
other
14
A JSON library implemented in VHDL.
fpga ghdl json vhdl parser xilinx lattice modelsim questasim synthesis fileformat simulation
Created 2015-09-01
61 commits to master branch, last one 2 years ago
stnolting
neorv32-verilog stnolting
13
70
bsd-3-clause
9
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
asic fpga ghdl neorv32 verilog icarus-verilog
Created 2022-08-27
321 commits to main branch, last one 5 days ago
stnolting
neorv32-setups stnolting
18
65
bsd-3-clause
8
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
soc fpga ghdl vhdl intel yosys risc-v xilinx lattice neorv32 verilog
Created 2022-01-11
518 commits to main branch, last one 4 days ago
tmeissner
psl_with_ghdl tmeissner
3
63
lgpl-3.0
11
Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
psl ghdl vhdl yosys assertions symbiyosys formal-verification functional-coverage
Created 2020-05-02
114 commits to master branch, last one about a year ago
mnemocron
my-discrete-fpga mnemocron
1
40
gpl-3.0
3
My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.
7400 fpga ghdl vhdl fpga-soc breadboard-computer
Created 2023-09-04
93 commits to main branch, last one 8 months ago