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An Open-source FPGA IP Generator
Created
2018-06-14
7,375 commits to master branch, last one 2 days ago
An Open Source configuration of the Arty platform
Created
2016-09-26
398 commits to master branch, last one 3 years ago
The Task Parallel System Composer (TaPaSCo)
Created
2019-01-15
2,392 commits to master branch, last one about a month ago
An AXI4 crossbar implementation in SystemVerilog
Created
2021-09-23
50 commits to main branch, last one 13 days ago
PYNQ example of using the RFSoC as a QPSK transceiver.
Created
2019-01-15
174 commits to master branch, last one about a year ago
Yet Another RISC-V Implementation
Created
2014-03-17
179 commits to master branch, last one 4 months ago
RFSoC Spectrum Analyser Module on PYNQ.
Created
2020-02-21
156 commits to master branch, last one about a year ago
Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
Created
2022-04-30
45 commits to main branch, last one about a year ago
SoftCPU/SoC engine-V
Created
2018-10-19
61 commits to master branch, last one 12 months ago
A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw
Created
2022-09-16
5 commits to master branch, last one about a year ago
[SIGCOMM 2023] Lightning: A Reconfigurable Photonic-Electronic SmartNIC for Fast and Energy-Efficient Inference
Created
2023-05-31
23 commits to main branch, last one 6 months ago
Intel Quartus Prime Synthesis Engine for Docker
Created
2022-07-25
12 commits to master branch, last one 3 months ago