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148
gpl-3.0
10
Logisim Italian Fork
Created 2017-04-21
428 commits to master branch, last one 2 years ago
IceChips is a library of all common discrete logic devices in Verilog
Created 2017-12-31
100 commits to main branch, last one a day ago
My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.
Created 2023-09-04
93 commits to main branch, last one 7 months ago