TimRudy / ice-chips-verilog

IceChips is a library of all common discrete logic devices in Verilog

Date Created 2017-12-31 (7 years ago)

Commits 100 (last one 3 months ago)

Stargazers 140 (0 this week)

Watchers 13 (0 this week)

Forks 24

License gpl-3.0

Ranking

RepositoryStats indexes 626,055 repositories, of these TimRudy/ice-chips-verilog is ranked #241,096 (61st percentile) for total stargazers, and #161,189 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #176/610.

TimRudy/ice-chips-verilog is also tagged with popular topics, for these it's ranked: fpga (#207/507), eda (#75/146)

Other Information

TimRudy/ice-chips-verilog has 1 open pull request on Github, 1 pull request has been merged over the lifetime of the repository.

Github issues are enabled, there are 4 open issues and 3 closed issues.

There have been 3 releases, the latest one was published on 2023-01-22 (2 years ago) with the name IceChips TTL Standard Parts Collection.

All Topics

eda 7400 fpga icestorm iverilog digital-logic logic-circuit open-hardware verilog-components

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

8 commits on the default branch (main) since jan '22

Yearly Commits

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2025-03-12 @ 10:01am, id: 115837888 / R_kgDOBueLwA