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VeeR EH1 core
Created
2019-06-02
125 commits to main branch, last one about a year ago
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
Created
2022-03-01
835 commits to main branch, last one 4 months ago
QKeras: a quantization deep learning library for Tensorflow Keras
Created
2019-08-06
439 commits to master branch, last one 14 days ago
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Created
2017-03-28
49 commits to master branch, last one 6 months ago
VeeR EL2 Core
Created
2020-01-09
686 commits to main branch, last one a day ago
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
Created
2021-11-21
98 commits to main branch, last one 11 days ago
Convolutional accelerator kernel, target ASIC & FPGA
Created
2021-06-21
2 commits to main branch, last one 3 years ago
IC implementation of Systolic Array for TPU
Created
2021-01-07
67 commits to main branch, last one 16 days ago
Open Application-Specific Instruction Set processor tools (OpenASIP)
Created
2015-10-22
4,471 commits to main branch, last one 6 months ago
Standard Cell Library based Memory Compiler using FF/Latch cells
Created
2020-11-09
281 commits to main branch, last one 10 months ago
An AXI4 crossbar implementation in SystemVerilog
Created
2021-09-23
50 commits to main branch, last one 5 months ago
hardware design of universal NPU(CNN accelerator) for various convolution neural network
Created
2023-07-18
162 commits to main branch, last one a day ago
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
Created
2020-07-12
1,137 commits to master branch, last one 3 months ago
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has ...
Created
2022-01-06
89 commits to main branch, last one 11 months ago
KiCad symbol library for sky130 and gf180mcu PDKs
Created
2023-10-05
55 commits to main branch, last one 8 months ago