15 results found Sort:

hughperkins
VeriGPU hughperkins
106
943
mit
32
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
gpu risc-v verilog asic-design verification risc-v-assembly gpu-acceleration hardware-designs machine-learning
Created 2022-03-01
841 commits to main branch, last one 3 months ago
chipsalliance
Cores-VeeR-EH1 chipsalliance
228
860
apache-2.0
57
VeeR EH1 core
rtl axi4 fpga risc veer riscv risc-v fusesoc riscv32 ahb-lite processor verilator asic-design western-digital open-source-hardware
Created 2019-06-02
125 commits to main branch, last one 2 years ago
google
qkeras google
104
557
apache-2.0
30
QKeras: a quantization deep learning library for Tensorflow Keras
fpga keras tensorflow accelerator asic-design quantization deep-learning fpga-accelerator machine-learning quantized-networks hardware-acceleration quantized-neural-networks
Created 2019-08-06
448 commits to master branch, last one about a month ago
dpretet
async_fifo dpretet
83
313
other
11
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
cdc hdl asic fifo fpga async verilog synthesis verilator fifo-cache fifo-queue asic-design verilog-hdl verification icarus-verilog cross-clock-domain
Created 2017-03-28
49 commits to master branch, last one 11 months ago
chipsalliance
Cores-VeeR-EL2 chipsalliance
79
266
apache-2.0
26
VeeR EL2 Core
el2 rtl axi4 fpga riscv risc-v fusesoc riscv32 ahb-lite processor verilator asic-design western-digital open-source-hardware
Created 2020-01-09
1,134 commits to main branch, last one a day ago
abdelazeem201
Systolic-array-implementation-in-RTL-for-TPU abdelazeem201
26
199
mit
3
IC implementation of Systolic Array for TPU
rtl asic fpga verilog asic-design asic-verification
Created 2021-01-07
67 commits to main branch, last one 4 months ago
lirui-shanghaitech
CNN-Accelerator-VLSI lirui-shanghaitech
29
185
apache-2.0
2
Convolutional accelerator kernel, target ASIC & FPGA
cnn fpga accelerator asic-design cnn-digital cnn-accelerator fpga-accelerator
Created 2021-06-21
2 commits to main branch, last one 3 years ago
stnolting
neoTRNG stnolting
22
177
bsd-3-clause
5
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
hdl rng rtl asic fpga trng vhdl chaos random entropy neorv32 asic-design cryptography key-generator entropy-source ring-oscillator random-number-generators
Created 2021-11-21
103 commits to main branch, last one about a month ago
cpc
openasip cpc
46
153
other
15
Open Application-Specific Instruction Set processor tools (OpenASIP)
fpga asic-design hardware-designs hardware-accelerators
Created 2015-10-22
4,488 commits to main branch, last one about a month ago
AUCOHL
DFFRAM AUCOHL
33
143
apache-2.0
13
Standard Cell Library based Memory Compiler using FF/Latch cells
vlsi verilog asic-design vlsi-circuits electronics-design vlsi-physical-design
Created 2020-11-09
281 commits to main branch, last one about a year ago
dpretet
axi-crossbar dpretet
27
137
mit
3
An AXI4 crossbar implementation in SystemVerilog
arm soc amba asic axi4 fpga riscv riscv32 riscv64 verilog crossbar fpga-soc monodraw axi4-full axi4-lite processor asic-design interconnect axi4-protocol
Created 2021-09-23
58 commits to main branch, last one 24 days ago
thousrm
universal_NPU-CNN_accelerator thousrm
13
107
mit
2
hardware design of universal NPU(CNN accelerator) for various convolution neural network
cnn npu verilog asic-design cnn-accelerator hardware-design
Created 2023-07-18
186 commits to main branch, last one 10 days ago
KastnerRG
cgra4ml KastnerRG
10
73
apache-2.0
0
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
ai cnn dnn asic fpga hls4ml verilog axi-stream asic-design systemverilog neural-network
Created 2020-07-12
1,139 commits to master branch, last one about a month ago
abdelazeem201
Design-and-ASIC-Implementation-of-32-Point-FFT-Processor abdelazeem201
2
39
mit
1
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has ...
fft rtl soc asic fpga vhdl verilog synthesis asic-design asic-verification
Created 2022-01-06
89 commits to main branch, last one about a year ago
lethalbit
kicad-pdk-libs lethalbit
1
32
apache-2.0
1
KiCad symbol library for sky130 and gf180mcu PDKs
kicad spice asic-design electronics
Created 2023-10-05
55 commits to main branch, last one about a year ago