chipsalliance / Cores-VeeR-EL2

VeeR EL2 Core

Date Created 2020-01-09 (4 years ago)

Commits 709 (last one a day ago)

Stargazers 250 (-1 this week)

Watchers 27 (0 this week)

Forks 75

License apache-2.0

Ranking

RepositoryStats indexes 585,332 repositories, of these chipsalliance/Cores-VeeR-EL2 is ranked #152,410 (74th percentile) for total stargazers, and #81,390 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #35/173.

chipsalliance/Cores-VeeR-EL2 is also tagged with popular topics, for these it's ranked: fpga (#127/478), risc-v (#81/263), riscv (#65/166)

Other Information

chipsalliance/Cores-VeeR-EL2 has 14 open pull requests on Github, 143 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 22 open issues and 59 closed issues.

Homepage URL: https://chipsalliance.github.io/Cores-VeeR-EL2/html/

All Topics

el2 rtl axi4 fpga riscv risc-v fusesoc riscv32 ahb-lite processor verilator asic-design western-digital open-source-hardware

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

669 commits on the default branch (main) since jan '22

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Issue History

Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-11-23 @ 12:04am, id: 232916517 / R_kgDODeIGJQ