chipsalliance / Cores-VeeR-EL2

VeeR EL2 Core

Date Created 2020-01-09 (5 years ago)
Commits 1,106 (last one 2 days ago)
Stargazers 263 (0 this week)
Watchers 27 (0 this week)
Forks 78
License apache-2.0
Ranking

RepositoryStats indexes 618,350 repositories, of these chipsalliance/Cores-VeeR-EL2 is ranked #151,992 (75th percentile) for total stargazers, and #82,300 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #34/192.

chipsalliance/Cores-VeeR-EL2 is also tagged with popular topics, for these it's ranked: fpga (#127/503),  risc-v (#81/271),  riscv (#66/175)

Other Information

chipsalliance/Cores-VeeR-EL2 has 1 open pull request on Github, 235 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 19 open issues and 64 closed issues.

Homepage URL: https://chipsalliance.github.io/Cores-VeeR-EL2/html/main/docs_rendered/html/index.html

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

1,066 commits on the default branch (main) since jan '22

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Yearly Commits

Commits to the default branch (main) per year

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Issue History

Total Issues
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Languages

The primary language is SystemVerilog but there's also others...

SystemVerilogSystemVerilogPythonPythonCCPerlPerlVerilogVerilogAssemblyAssemblyMakefileMakefileRobotFrameworkRobotFrameworkTclTclShellShellOtherOther

updated: 2025-02-21 @ 06:11pm, id: 232916517 / R_kgDODeIGJQ