115 results found Sort:

MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use L...
Created 2015-06-13
387 commits to master branch, last one about a year ago
597
4.0k
apache-2.0
150
Chisel: A Modern Hardware Design Language
Created 2015-04-27
6,151 commits to main branch, last one 5 days ago
1.1k
3.2k
other
197
Rocket Chip Generator
Created 2014-09-12
8,971 commits to master branch, last one about a month ago
607
2.5k
lgpl-3.0
70
Verilator open-source SystemVerilog simulator and lint system
Created 2019-06-13
7,393 commits to master branch, last one 2 days ago
144
2.4k
mit
43
Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]
Created 2017-02-28
1,075 commits to master branch, last one 9 months ago
285
2.1k
bsd-3-clause
94
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Created 2018-08-19
341 commits to master branch, last one 27 days ago
425
1.7k
bsd-3-clause
87
SonicBOOM: The Berkeley Out-of-Order Machine
Created 2014-01-21
2,345 commits to master branch, last one about a month ago
Framework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)
Created 2014-03-04
426 commits to master branch, last one 2 months ago
331
1.7k
other
80
Scala based HDL
Created 2015-01-25
7,369 commits to dev branch, last one a day ago
648
1.6k
bsd-3-clause
86
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Created 2016-10-24
4,976 commits to main branch, last one 15 hours ago
224
1.6k
bsd-3-clause
50
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Created 2020-06-23
7,442 commits to main branch, last one 4 days ago
552
1.6k
bsd-3-clause
52
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Created 2019-10-28
25,183 commits to master branch, last one 12 hours ago
373
1.4k
apache-2.0
59
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Created 2020-07-20
1,892 commits to master branch, last one about a month ago
265
1.1k
other
39
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Created 2018-04-12
1,296 commits to master branch, last one 13 days ago
A simple yet powerful JQuery star rating plugin with fractional rating support.
Created 2014-02-25
263 commits to master branch, last one about a year ago
275
859
other
51
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Created 2017-05-09
66 commits to master branch, last one about a month ago
112
818
unknown
54
Salamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.
Created 2016-09-30
41 commits to master branch, last one 3 years ago
221
818
apache-2.0
58
VeeR EH1 core
Created 2019-06-02
125 commits to main branch, last one about a year ago
170
763
apache-2.0
33
:earth_africa: Map location picker component for Android. Based on Google Maps. An alternative to Google Place Picker.
Created 2016-07-27
441 commits to master branch, last one about a month ago
213
703
unknown
48
Various HDL (Verilog) IP Cores
Created 2015-05-30
54 commits to master branch, last one 3 years ago
237
696
agpl-3.0
43
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
Created 2019-12-05
333 commits to master branch, last one 11 months ago
197
614
agpl-3.0
7
⚡ Full RTL Package - Bootstrap Responsive Components For Iranian's 🇮🇷
Created 2023-03-06
87 commits to main branch, last one 26 days ago
An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器...
Created 2020-09-04
29 commits to main branch, last one about a year ago
110
546
other
37
Simple RISC-V 3-stage Pipeline in Chisel
This repository has been archived (exclude archived)
Created 2016-09-28
223 commits to main branch, last one 5 months ago
A library which configures a divider for a RecyclerView.
Created 2016-04-12
456 commits to master branch, last one 7 months ago
24
505
other
12
Veryl: A Modern Hardware Description Language
Created 2022-12-08
2,166 commits to master branch, last one a day ago
94
491
unknown
38
A curated list of awesome projects and dev/design resources for supporting Arabic computational needs.
Created 2015-09-19
95 commits to master branch, last one 2 months ago
RTL edition of bootstrap v4 for rtl languages like Farsi and Arabic
Created 2016-04-01
241 commits to main branch, last one 24 days ago
12
398
agpl-3.0
4
⭕️ نپرس که بپرسم، فقط بپرس ⭕️
Created 2020-09-19
84 commits to master branch, last one about a year ago
50
391
gpl-2.0
24
bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
Created 2020-12-31
14 commits to main branch, last one 6 months ago