Search Results - RepositoryStats

893

4.4k

mit

164

MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use L...

Created 2015-06-13

387 commits to master branch, last one 9 months ago

chisel chipsalliance

574

3.8k

apache-2.0

148

Chisel: A Modern Hardware Design Language

rtl scala chisel firrtl chisel3 verilog chip-generator

Created 2015-04-27

5,921 commits to main branch, last one 13 hours ago

rocket-chip chipsalliance

1.1k

3.0k

other

197

Rocket Chip Generator

rtl riscv scala chisel rocket-chip chip-generator

Created 2014-09-12

8,667 commits to master branch, last one 2 months ago

PinLayout layoutBox

142

2.3k

mit

44

Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]

ios rtl swift anchor ios-ui layout margin ios-lib swift-3 carthage cocoapod language ios-swift layout-engine left-language swift-library swift-framework uiview-extension chainable-methods

Created 2017-02-28

1,075 commits to master branch, last one 4 months ago

verilator verilator

544

2.2k

lgpl-3.0

74

Verilator open-source SystemVerilog simulator and lint system

cpp rtl systemc verilog compilers verilator system-verilog verilog-simulator

Created 2019-06-13

6,963 commits to master branch, last one a day ago

darkriscv darklife

270

1.9k

bsd-3-clause

86

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

cpu rtl core fpga riscv rv32e rv32i risc-v verilog softcore processor processor-design

Created 2018-08-19

282 commits to master branch, last one 7 days ago

rtlcss MohammadYounes

127

1.7k

mit

39

Framework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)

css ltr rtl css3 flip i18n mirror rtlcss postcss left-to-right right-to-left postcss-plugin cascading-style-sheets

Created 2014-03-04

421 commits to master branch, last one 4 months ago

riscv-boom riscv-boom

405

1.6k

bsd-3-clause

84

SonicBOOM: The Berkeley Out-of-Order Machine

rtl boom riscv scala chisel berkeley riscv-boom rocket-chip

Created 2014-01-21

2,320 commits to master branch, last one 14 days ago

SpinalHDL SpinalHDL

302

1.5k

other

78

Scala based HDL

rtl fpga vhdl scala verilog

Created 2015-01-25

6,813 commits to dev branch, last one a day ago

chipyard ucb-bar

598

1.5k

bsd-3-clause

82

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

rtl soc boom riscv chisel hwacha risc-v rocket firesim chipyard peripherals rocket-chip superscalar accelerators out-of-order chip-generator

Created 2016-10-24

4,613 commits to main branch, last one a day ago

neorv32 stnolting

201

1.5k

bsd-3-clause

49

:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Created 2020-06-23

6,554 commits to main branch, last one 17 hours ago

OpenROAD The-OpenROAD-Project

484

1.4k

bsd-3-clause

55

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

cpp def eda lef rtl tcl gdsii verilog openroad opendb-database timing-analysis

Created 2019-10-28

22,266 commits to master branch, last one 12 hours ago

OpenLane The-OpenROAD-Project

359

1.2k

apache-2.0

58

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

rtl asic vlsi 130nm magic yosys netgen caravel foundry klayout openram rtl2gds verilog openroad skywater soc-design system-on-chip

Created 2020-07-20

1,877 commits to master branch, last one 4 days ago

bootstrap-star-rating kartik-v

400

1.0k

other

66

A simple yet powerful JQuery star rating plugin with fractional rating support.

css rtl star jquery rating caption css-styles fractional javascript change-stars rate-control star-symbols bootstrap-star-rating

Created 2014-02-25

263 commits to master branch, last one about a year ago

axi pulp-platform

242

951

other

38

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

ip axi rtl asic axi4 fpga hardware axi4-lite systemverilog network-on-chip

Created 2018-04-12

1,248 commits to master branch, last one 23 days ago

Salamandra eldraco

116

816

unknown

54

Salamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.

rtl sdr spy sound python threshold microphone salamandra microphones spy-microphones find-microphones detect-microphones

Created 2016-09-30

41 commits to master branch, last one 3 years ago

scr1 syntacore

267

789

other

49

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

ip rtl core riscv rv32e rv32i risc-v rv32emc rv32imc verilog

Created 2017-05-09

65 commits to master branch, last one 25 days ago

Cores-VeeR-EH1 chipsalliance

207

779

apache-2.0

57

VeeR EH1 core

rtl axi4 fpga risc veer riscv risc-v fusesoc riscv32 ahb-lite processor verilator asic-design western-digital open-source-hardware

Created 2019-06-02

125 commits to main branch, last one about a year ago

Leku AdevintaSpain

175

757

apache-2.0

33

:earth_africa: Map location picker component for Android. Based on Google Maps. An alternative to Google Place Picker.

Created 2016-07-27

432 commits to master branch, last one 4 months ago

cores ultraembedded

199

645

unknown

47

Various HDL (Verilog) IP Cores

i2s rtl spi usb asic fpga sram uart audio sdram verilog verilator verilog-hdl verilog-components

Created 2015-05-30

54 commits to master branch, last one 2 years ago

openwifi-hw open-sdr

219

639

agpl-3.0

41

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

dma hls rtl sdr csma fpga ofdm vhdl zynq linux wi-fi ad9361 xilinx verilog hardware mac80211 ieee80211 analog-devices software-defined-radio

Created 2019-12-05

333 commits to master branch, last one 6 months ago

recycler-view-divider fondesa

44

507

apache-2.0

8

A library which configures a divider for a RecyclerView.

rtl list android divider androidx staggered recyclerview staggeredgrid itemdecoration gridlayoutmanager linearlayoutmanager divideritemdecoration staggeredgridlayoutmanager

Created 2016-04-12

456 commits to master branch, last one 2 months ago

riscv-mini ucb-bar

100

504

other

39

Simple RISC-V 3-stage Pipeline in Chisel

rtl riscv chisel

Created 2016-09-28

222 commits to main branch, last one 2 months ago

FPGA-USB-Device WangXuan95

81

488

gpl-3.0

23

An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器...

Created 2020-09-04

29 commits to main branch, last one 8 months ago

awesome-arabic 01walid

92

476

unknown

38

A curated list of awesome projects and dev/design resources for supporting Arabic computational needs.

nlp rtl arabic nlp-arabic natural-language-processing

Created 2015-09-19

93 commits to master branch, last one about a year ago

bootstrap-v4-rtl MahdiMajidzadeh

171

465

mit

17

RTL edition of bootstrap v4 for rtl languages like Farsi and Arabic

rtl farsi arabic persian bootstrap rtl-edition css-framework right-to-left

Created 2016-04-01

229 commits to main branch, last one 2 months ago

Web-Package-RTL 4xmen

127

436

agpl-3.0

7

⚡ Full RTL Package - Bootstrap Responsive Components For Iranian's 🇮🇷

css rtl html sass 4xmen xstack persian components rtl-design rtl-package web-package full-package right-to-left rtl-component persian-template components-and-templates

Created 2023-03-06

82 commits to main branch, last one 2 months ago