Search Results - RepositoryStats

899

4.4k

mit

164

MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use L...

Created 2015-06-13

387 commits to master branch, last one about a year ago

chisel chipsalliance

606

4.0k

apache-2.0

153

Chisel: A Modern Hardware Design Language

rtl scala chisel firrtl chisel3 verilog chip-generator

Created 2015-04-27

6,225 commits to main branch, last one a day ago

rocket-chip chipsalliance

1.1k

3.3k

other

197

Rocket Chip Generator

rtl riscv scala chisel rocket-chip chip-generator

Created 2014-09-12

8,973 commits to master branch, last one about a month ago

verilator verilator

625

2.6k

lgpl-3.0

73

Verilator open-source SystemVerilog simulator and lint system

cpp rtl systemc verilog compilers verilator system-verilog verilog-simulator

Created 2019-06-13

7,537 commits to master branch, last one a day ago

PinLayout layoutBox

144

2.4k

mit

43

Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]

ios rtl swift anchor ios-ui layout margin ios-lib swift-3 carthage cocoapod language ios-swift layout-engine left-language swift-library swift-framework uiview-extension chainable-methods

Created 2017-02-28

1,075 commits to master branch, last one 11 months ago

darkriscv darklife

290

2.1k

bsd-3-clause

94

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

cpu rtl core fpga riscv rv32e rv32i risc-v verilog softcore processor processor-design

Created 2018-08-19

343 commits to master branch, last one about a month ago

riscv-boom riscv-boom

426

1.8k

bsd-3-clause

87

SonicBOOM: The Berkeley Out-of-Order Machine

rtl boom riscv scala chisel berkeley riscv-boom rocket-chip

Created 2014-01-21

2,345 commits to master branch, last one 2 months ago

chipyard ucb-bar

663

1.7k

bsd-3-clause

88

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

rtl soc boom riscv chisel hwacha risc-v rocket firesim chipyard peripherals rocket-chip superscalar accelerators out-of-order chip-generator

Created 2016-10-24

4,995 commits to main branch, last one 15 days ago

SpinalHDL SpinalHDL

336

1.7k

other

81

Scala based HDL

rtl fpga vhdl scala verilog

Created 2015-01-25

7,481 commits to dev branch, last one 2 days ago

rtlcss MohammadYounes

129

1.7k

mit

38

Framework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)

css ltr rtl css3 flip i18n mirror rtlcss postcss left-to-right right-to-left postcss-plugin cascading-style-sheets

Created 2014-03-04

426 commits to master branch, last one 3 months ago

OpenROAD The-OpenROAD-Project

577

1.7k

bsd-3-clause

54

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

cpp def eda lef rtl tcl gdsii verilog openroad opendb-database timing-analysis

Created 2019-10-28

26,016 commits to master branch, last one a day ago

neorv32 stnolting

231

1.6k

bsd-3-clause

52

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Created 2020-06-23

7,619 commits to main branch, last one a day ago

OpenLane The-OpenROAD-Project

379

1.4k

apache-2.0

61

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

rtl asic vlsi 130nm magic yosys netgen caravel foundry klayout openram rtl2gds verilog openroad skywater soc-design system-on-chip

Created 2020-07-20

1,892 commits to master branch, last one 2 months ago

axi pulp-platform

272

1.1k

other

39

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

ip axi rtl asic axi4 fpga hardware axi4-lite systemverilog network-on-chip

Created 2018-04-12

1,311 commits to master branch, last one 3 days ago

bootstrap-star-rating kartik-v

398

1.1k

other

66

A simple yet powerful JQuery star rating plugin with fractional rating support.

css rtl star jquery rating caption css-styles fractional javascript change-stars rate-control star-symbols bootstrap-star-rating

Created 2014-02-25

263 commits to master branch, last one about a year ago

scr1 syntacore

282

883

other

52

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

ip rtl core riscv rv32e rv32i risc-v rv32emc rv32imc verilog

Created 2017-05-09

67 commits to master branch, last one about a month ago

Cores-VeeR-EH1 chipsalliance

221

831

apache-2.0

58

VeeR EH1 core

rtl axi4 fpga risc veer riscv risc-v fusesoc riscv32 ahb-lite processor verilator asic-design western-digital open-source-hardware

Created 2019-06-02

125 commits to main branch, last one 2 years ago

Salamandra eldraco

112

820

unknown

54

Salamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.

rtl sdr spy sound python threshold microphone salamandra microphones spy-microphones find-microphones detect-microphones

Created 2016-09-30

41 commits to master branch, last one 3 years ago

Leku AdevintaSpain

171

767

apache-2.0

33

:earth_africa: Map location picker component for Android. Based on Google Maps. An alternative to Google Place Picker.

Created 2016-07-27

441 commits to master branch, last one 2 months ago

cores ultraembedded

215

716

unknown

48

Various HDL (Verilog) IP Cores

i2s rtl spi usb asic fpga sram uart audio sdram verilog verilator verilog-hdl verilog-components

Created 2015-05-30

54 commits to master branch, last one 3 years ago

openwifi-hw open-sdr

240

709

agpl-3.0

43

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

dma hls rtl sdr csma fpga ofdm vhdl zynq linux wi-fi ad9361 xilinx verilog hardware mac80211 ieee80211 analog-devices software-defined-radio

Created 2019-12-05

334 commits to master branch, last one 20 days ago

FPGA-USB-Device WangXuan95

107

638

lgpl-2.1

28

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed...

Created 2020-09-04

31 commits to main branch, last one 14 days ago

Web-Package-RTL 4xmen

201

635

agpl-3.0

7

⚡ Full RTL Package - Bootstrap Responsive Components For Iranian's 🇮🇷

css rtl html sass 4xmen xstack persian components rtl-design rtl-package web-package full-package right-to-left rtl-component persian-template components-and-templates

Created 2023-03-06

87 commits to main branch, last one 2 months ago

riscv-mini ucb-bar

112

552

other

38

Simple RISC-V 3-stage Pipeline in Chisel

rtl riscv chisel

This repository has been archived (exclude archived)

Created 2016-09-28

223 commits to main branch, last one 6 months ago

veryl veryl-lang

27

550

other

13

Veryl: A Modern Hardware Description Language

hdl rtl rust verilog systemverilog

Created 2022-12-08

2,319 commits to master branch, last one 2 days ago

recycler-view-divider fondesa

45

510

apache-2.0

8

A library which configures a divider for a RecyclerView.

rtl list android divider androidx staggered recyclerview staggeredgrid itemdecoration gridlayoutmanager linearlayoutmanager divideritemdecoration staggeredgridlayoutmanager

Created 2016-04-12

456 commits to master branch, last one 8 months ago