115 results found Sort:
MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use L...
Created
2015-06-13
387 commits to master branch, last one about a year ago
Chisel: A Modern Hardware Design Language
Created
2015-04-27
6,151 commits to main branch, last one 5 days ago
Rocket Chip Generator
Created
2014-09-12
8,971 commits to master branch, last one about a month ago
Verilator open-source SystemVerilog simulator and lint system
Created
2019-06-13
7,393 commits to master branch, last one 2 days ago
Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]
Created
2017-02-28
1,075 commits to master branch, last one 9 months ago
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Created
2018-08-19
341 commits to master branch, last one 27 days ago
SonicBOOM: The Berkeley Out-of-Order Machine
Created
2014-01-21
2,345 commits to master branch, last one about a month ago
Framework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)
Created
2014-03-04
426 commits to master branch, last one 2 months ago
Scala based HDL
Created
2015-01-25
7,369 commits to dev branch, last one a day ago
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Created
2016-10-24
4,976 commits to main branch, last one 15 hours ago
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Created
2020-06-23
7,442 commits to main branch, last one 4 days ago
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Created
2019-10-28
25,183 commits to master branch, last one 12 hours ago
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Created
2020-07-20
1,892 commits to master branch, last one about a month ago
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Created
2018-04-12
1,296 commits to master branch, last one 13 days ago
A simple yet powerful JQuery star rating plugin with fractional rating support.
Created
2014-02-25
263 commits to master branch, last one about a year ago
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Created
2017-05-09
66 commits to master branch, last one about a month ago
Salamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.
Created
2016-09-30
41 commits to master branch, last one 3 years ago
VeeR EH1 core
Created
2019-06-02
125 commits to main branch, last one about a year ago
:earth_africa: Map location picker component for Android. Based on Google Maps. An alternative to Google Place Picker.
Created
2016-07-27
441 commits to master branch, last one about a month ago
Various HDL (Verilog) IP Cores
Created
2015-05-30
54 commits to master branch, last one 3 years ago
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
Created
2019-12-05
333 commits to master branch, last one 11 months ago
⚡ Full RTL Package - Bootstrap Responsive Components For Iranian's 🇮🇷
Created
2023-03-06
87 commits to main branch, last one 26 days ago
An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器...
Created
2020-09-04
29 commits to main branch, last one about a year ago
Simple RISC-V 3-stage Pipeline in Chisel
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Created
2016-09-28
223 commits to main branch, last one 5 months ago
A library which configures a divider for a RecyclerView.
Created
2016-04-12
456 commits to master branch, last one 7 months ago
Veryl: A Modern Hardware Description Language
Created
2022-12-08
2,166 commits to master branch, last one a day ago
A curated list of awesome projects and dev/design resources for supporting Arabic computational needs.
Created
2015-09-19
95 commits to master branch, last one 2 months ago
RTL edition of bootstrap v4 for rtl languages like Farsi and Arabic
Created
2016-04-01
241 commits to main branch, last one 24 days ago
⭕️ نپرس که بپرسم، فقط بپرس ⭕️
Created
2020-09-19
84 commits to master branch, last one about a year ago
bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
Created
2020-12-31
14 commits to main branch, last one 6 months ago