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The-OpenROAD-Project
OpenLane The-OpenROAD-Project
375
1.4k
apache-2.0
60
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
rtl asic vlsi 130nm magic yosys netgen caravel foundry klayout openram rtl2gds verilog openroad skywater soc-design system-on-chip
Created 2020-07-20
1,892 commits to master branch, last one about a month ago
efabless
caravel efabless
69
295
apache-2.0
21
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
magic yosys sky130 caravel openram openroad picorv32 vexriscv
Created 2021-10-07
1,607 commits to main branch, last one 19 days ago
efabless
caravel_mpw-one efabless
136
135
apache-2.0
17
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
magic yosys sky130 caravel openram openroad picorv32
Created 2020-11-12
1,100 commits to master branch, last one 3 years ago