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Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Created
2020-05-06
370 commits to main branch, last one about a year ago
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Created
2020-07-20
1,879 commits to master branch, last one 3 days ago
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
Created
2021-10-07
1,592 commits to main branch, last one 29 days ago
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
Created
2020-11-12
1,100 commits to master branch, last one 2 years ago
Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
Created
2021-02-06
57 commits to main branch, last one 3 years ago