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OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Created
2020-07-20
1,879 commits to master branch, last one 3 days ago
Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description and software programming languages
Created
2021-11-18
22 commits to main branch, last one 7 months ago