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379

1.4k

apache-2.0

61

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

rtl asic vlsi 130nm magic yosys netgen caravel foundry klayout openram rtl2gds verilog openroad skywater soc-design system-on-chip

Created 2020-07-20

1,892 commits to master branch, last one 2 months ago

Advanced-System-on-Chip-Design-Education-Kit arm-university

30

85

unknown

6

Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description and software programming languages

arm amba fpga armv7 cortex-a cortex-a9 soc-design zybo-z7-10 arm-cortex-a9 hardware-designs system-on-chip-design

Created 2021-11-18

23 commits to main branch, last one 4 months ago

Fundamentals-of-System-on-Chip-Design-on-Arm-Cortex-M-Microcontrollers arm-university

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27

other

1

A textbook on understanding system on chip design

soc amba fpga cmsis fpga-soc textbook trustzone soc-design arm-cortex-m bus-architecture cpu-architecture embedded-systems system-on-chip-design

Created 2023-03-21

19 commits to main branch, last one about a year ago