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368

1.3k

apache-2.0

59

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

rtl asic vlsi 130nm magic yosys netgen caravel foundry klayout openram rtl2gds verilog openroad skywater soc-design system-on-chip

Created 2020-07-20

1,890 commits to master branch, last one 6 days ago

avsdpll_1v8 lakshmi-sathi

42

108

gpl-2.0

13

8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperat...

ic pll asic rtl2gds charge-pump analog-circuit manufacturable phase-detector clock-multiplier intellectual-property

Created 2020-10-28

384 commits to main branch, last one 3 years ago

OpenLANE-Sky130-Physical-Design-Workshop AngeloJacobo

15

46

mit

2

Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

asic vlsi sky130 rtl2gds openlane openlane-flow vlsi-physical-design

Created 2022-08-04

150 commits to main branch, last one 2 years ago