The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Date Created 2020-07-20 (3 years ago)

Commits 1,879 (last one 3 days ago)

Stargazers 1,250 (6 this week)

Watchers 58 (0 this week)

Forks 365

License apache-2.0

Ranking

RepositoryStats indexes 534,551 repositories, of these The-OpenROAD-Project/OpenLane is ranked #39,394 (93rd percentile) for total stargazers, and #34,427 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #5,953/103,470.

The-OpenROAD-Project/OpenLane is also tagged with popular topics, for these it's ranked: verilog (#19/257)

Other Information

The-OpenROAD-Project/OpenLane has 1 open pull request on Github, 816 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 148 open issues and 793 closed issues.

Homepage URL: https://openlane.readthedocs.io/

All Topics

rtl asic vlsi 130nm magic yosys netgen caravel foundry klayout openram rtl2gds verilog openroad skywater soc-design system-on-chip

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

476 commits on the default branch (master) since jan '22

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Languages

The primary language is Python but there's also others...

updated: 2024-06-28 @ 09:29pm, id: 281208911 / R_kgDOEMLoTw