The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Date Created 2020-07-20 (4 years ago)

Commits 1,892 (last one about a month ago)

Stargazers 1,367 (6 this week)

Watchers 60 (0 this week)

Forks 379

License apache-2.0

Ranking

RepositoryStats indexes 589,134 repositories, of these The-OpenROAD-Project/OpenLane is ranked #38,251 (94th percentile) for total stargazers, and #33,510 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #5,907/117,584.

The-OpenROAD-Project/OpenLane is also tagged with popular topics, for these it's ranked: verilog (#19/284)

Other Information

The-OpenROAD-Project/OpenLane has 3 open pull requests on Github, 829 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 89 open issues and 871 closed issues.

Homepage URL: https://openlane.readthedocs.io/

All Topics

rtl asic vlsi 130nm magic yosys netgen caravel foundry klayout openram rtl2gds verilog openroad skywater soc-design system-on-chip

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

489 commits on the default branch (master) since jan '22

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Languages

The primary language is Python but there's also others...

updated: 2024-12-03 @ 11:24am, id: 281208911 / R_kgDOEMLoTw