3 results found Sort:

The-OpenROAD-Project
OpenLane The-OpenROAD-Project
392
1.4k
apache-2.0
62
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
rtl asic vlsi 130nm magic yosys netgen caravel foundry klayout openram rtl2gds verilog openroad skywater soc-design system-on-chip
Created 2020-07-20
1,893 commits to master branch, last one 3 months ago
VLSIDA
OpenRAM VLSIDA
218
883
bsd-3-clause
56
An open-source static random access memory (SRAM) compiler.
gds sram magic netgen python ngspice netlists
Created 2016-11-02
4,867 commits to stable branch, last one about a year ago
iic-jku
osic-multitool iic-jku
16
58
apache-2.0
12
JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.
lvs magic netgen sky130 xschem ngspice openlane
Created 2021-12-26
153 commits to main branch, last one a day ago