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An open-source static random access memory (SRAM) compiler.
Created
2016-11-02
4,867 commits to stable branch, last one 9 months ago
Various HDL (Verilog) IP Cores
Created
2015-05-30
54 commits to master branch, last one 3 years ago
Open Hardware SNES Cartridge with save capability
Created
2020-10-26
15 commits to master branch, last one 3 years ago
The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done using Cadence Virtuoso’s ADE, & the Static Nois...
Created
2019-03-27
4 commits to master branch, last one 2 years ago
A reading list for SRAM-based Compute-In-Memory (CIM) research.
Created
2024-02-01
6 commits to main branch, last one 2 months ago