ultraembedded / cores

Various HDL (Verilog) IP Cores

Date Created 2015-05-30 (9 years ago)

Commits 54 (last one 3 years ago)

Stargazers 710 (1 this week)

Watchers 48 (0 this week)

Forks 215

License unknown

Ranking

RepositoryStats indexes 585,332 repositories, of these ultraembedded/cores is ranked #69,504 (88th percentile) for total stargazers, and #43,577 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #32/535.

ultraembedded/cores is also tagged with popular topics, for these it's ranked: audio (#274/1491), fpga (#55/478), usb (#51/299), verilog (#37/282)

Other Information

ultraembedded/cores has 2 open pull requests on Github, 0 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there is 1 open issue and 4 closed issues.

All Topics

i2s rtl spi usb asic fpga sram uart audio sdram verilog verilator verilog-hdl verilog-components

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

0 commits on the default branch (master) since jan '22

No recent commits to this repository

Yearly Commits

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-11-19 @ 08:02am, id: 36567136 / R_kgDOAi34YA